PriME: A parallel and distributed simulator for thousand-core chips

Fu, Yaosheng; Wentzlaff, David

doi:10.1109/ispass.2014.6844467

Cited by 27 publications

(16 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In other words, they can not run applications such as multithreaded and JVM workloads that frequently use applications that are sensitive to system time like and client-server workloads. As examples of user/application level simulators we can mention SimpleScalar [9], BigSim [10], Graphite [11], Sniper [12], ZSim [13] and PriME [14].…”

Section: Terminology and Classificationsmentioning

confidence: 99%

“…In timing-directed organization, the architectural state in both (timing and functional) partitions are naturally matched with each other, thereby preventing execution divergence. Talisman [27], Graphite [11], ZSim [13] and PriME [14] use this organization. Simulator Execution: The execution of simulations on the host machines can be either sequential or parallel.…”

Section: Terminology and Classificationsmentioning

confidence: 99%

“…Most of the current instrumentation-based simulators run on x86 hosts, since x86 is common in both desktop and server segments, and the ISA's impact is less relevant. Examples using emulation strategies include MARSS [6], Gem5 [4], SimFlex, COTSon and BigSim while simulators such as CMPSim [46], Graphite [11], PriME [14], ZSim [13] and McSimA+ [69] benefit from instrumentation strategies.…”

Section: Terminology and Classificationsmentioning

confidence: 99%

“…Many of the current instrumentation-based simulators such as Graphite [11], PriME [14] and ZSim [13] benefit from DBT tools and libraries which leverage same-ISA DBT on x86 host architecture. Examples of these DBT systems include Pin [71], StarDBT [72], and DynamoRIO [73].…”

Section: Terminology and Classificationsmentioning

confidence: 99%

“…PriME [14] is an MPI-based, manycore, x86 simulator. It uses Pin as simulation engine and combines both shared memory and message passing techniques in order to achieve high parllelization and distribution of simulation workloads through running simulation across any MPI-enabled cluster of multiprocessor and multicore machines.…”

Section: Primementioning

confidence: 99%

See 4 more Smart Citations

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

View full text Add to dashboard Cite

This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

show abstract

Section: Terminology and Classificationsmentioning

confidence: 99%

Section: Terminology and Classificationsmentioning

confidence: 99%

Section: Terminology and Classificationsmentioning

confidence: 99%

Section: Terminology and Classificationsmentioning

confidence: 99%

Section: Primementioning

confidence: 99%

See 3 more Smart Citations

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

View full text Add to dashboard Cite

show abstract

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

View full text Add to dashboard Cite

In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

show abstract

Simulating the Network Activity of Modern Manycores

2019

View full text Add to dashboard Cite

Manycore architectures are one of the most promising candidates to reach the exascale. However, the increase in the number of cores on a single die exacerbates the memory wall problem. Modern manycore architectures integrate increasingly complex and heterogeneous memory systems to work around the memory bottleneck while increasing computational power. The Intel Mesh Interconnect architecture is the latest interconnect designed by Intel for its HPC product lines. Processors are organized in a rectangular network-on-chip (NoC), connected to several different memory interfaces, and using a distributed directory to guarantee coherent memory accesses. Since the traffic on the NoC is completely opaque to the programmer, simulation tools are needed to understand the performance trade-offs of code optimizations. Recently featured in Intel's Xeon Scalable lines, this interconnect was first included in the Knights Landing (KNL), a manycore processor with up to 72 cores. This work analyzes the behavior of the Intel Mesh Interconnect through the KNL architecture, proposing ways to discover the physical layout of its logical components. We have designed and developed an extension to the Tejas memory system simulator to replicate and study the low-level data traffic of the processor network. The reliability and accuracy of the proposed simulator is assessed using several state-of-the-art sequential and parallel benchmarks, and a particular Intel Mesh Interconnect-focused locality optimization is proposed and studied using the simulator and a real KNL system.

show abstract

PriME: A parallel and distributed simulator for thousand-core chips

Cited by 27 publications

References 30 publications

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Simulating the Network Activity of Modern Manycores

Contact Info

Product

Resources

About