Principles of new method of optimisation, design and modelling of pipeline A/D converters

A new approach to improvement of pipeline A/D converters characteristics

“…The result is worsening of the achievable resolution of PADC in comparison with the potentially available resolution [7][8][9].…”

“…The earlier research on application of these adaptive algorithms in pipeline A/D converters led to the architecture of the standard IP ADC presented in Fig. 3 [7][8][9], which is directly related to adaptive estimation algorithms proposed in [3]. D D − of SADC k , is defined as follows:…”

“…The approach comes from the analytical method of optimization of adaptive estimation systems based on the concept of a statistically fitted observation [3]. Application of these methods into A/D converters led to the development of new classes of converters, firstly so called intelligent cyclic A/D converters (IC ADC) [4][5][6] and next, intelligent pipeline A/D converters (IP ADC) [7][8][9].…”

“…The architecture of IP ADC enables application of the method of concurrent optimization of the analog and digital parts of the converter as a result of introduction of the long-bit codes and long-bit arithmetic for output codes computing instead of the common for conventional converters method of the codes computing in the form of a sum of shifted lowbit binary words delivered by sequential stages [7][8][9]. This creates a possibility to compute the output codes using optimal adaptive estimation algorithms and permits to remove, inevitable in conventional pipeline A/D converters, constraints on the values of amplifiers gains in particular stages of the converter, i.e.…”

“…The first attempt to application of the adaptive algorithms resulting from the analytical approach [3] in pipeline A/D converters led to the architecture and operation principles presented in [7][8][9] and called in this paper as the standard IP ADC. The main disadvantages of the standard IP ADC are related to the high requirements on the resolution of the D/A sub-converters and large values of amplifiers gains, increasing in subsequent stages of IP ADC and, in consequence, relatively complex structure of particular stages of IP ADC.…”