PRINS: Processing-in-Storage Acceleration of Machine Learning

Kaplan, Roman; Yavits, Leonid; Ginosar, Ran

doi:10.1109/tnano.2018.2799872

Cited by 34 publications

(11 citation statements)

References 45 publications

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“…SSD devices have finite endurance, meaning that the total number of writes to the device is fixed [25]. Traditional ISP architectures usually introduce more writes to SSD devices and thus could suffer from the endurance issue [27]. In comparison, the database in INSPIRE remains static in the protocol, and we avoid massive SSD writes by reducing the query size and buffering the query on-chip.…”

Section: Discussionmentioning

confidence: 99%

Inspire

Lin

Liang

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Private Information Retrieval (PIR) plays a vital role in secure, database-centric applications. However, existing PIR protocols explore a massive working space containing hundreds of GiBs of query and database data. As a consequence, PIR performance is severely bounded by storage communication, making it far from practical for real-world deployment.In this work, we describe INSPIRE, an accelerator for IN-Storage Private Information REtrieval. INSPIRE follows a protocol and architecture co-design approach. We first design the INSPIRE protocol with a multi-stage filtering mechanism, which achieves a constant PIR query size. For a 1-billion-entry database of size 288GiB, IN-SPIRE's protocol reduces the query size from 27GiB to 3.6MiB. Further, we propose the INSPIRE hardware, a heterogeneous instorage architecture, which integrates our protocol across the SSD hierarchy. Together with the INSPIRE protocol, the INSPIRE hardware reduces the query time from 28.4min to 36s, relative to the the state-of-the-art FastPIR scheme. CCS CONCEPTS• Hardware → Memory and dense storage; • Security and privacy → Data anonymization and sanitization.

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Section: Discussionmentioning

confidence: 99%

Inspire

Lin

Liang

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…Many ternary and binary NOR-and NAND-based CAM bitcell designs have been proposed in recent years, including both CMOSbased [2, 6, 14, 15, 17, 20ś22, 29, 33, 50, 60, 67, 75, 76] and emergingmemory-based [34,36,62,73,74] solutions. Several CAM designs offer soft-error tolerance using error correction coding (which requires memory redundancy) and replacing the matchline sense amplifier with an analog comparator [41,58].…”

Section: Approximate Search Content-addressable Memorymentioning

confidence: 99%

Edam

Hanhan

Garzón

Zuher

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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We propose a novel edit distance-tolerant content addressable memory (EDAM) for energy-efficient approximate search applications. Unlike state-of-the-art approximate search solutions that tolerate certain Hamming distance between the query pattern and the stored data, EDAM tolerates edit distance, which makes it especially efficient in applications such as text processing and genome analysis. EDAM was designed using a commercial 65 nm 1.2 V CMOS technology and evaluated through extensive Monte Carlo simulations, while considering different process corners. Simulation results show that EDAM can achieve robust approximate search operation with a wide range of edit distance threshold levels. EDAM is functionally evaluated as a pathogen DNA detection and classification accelerator. EDAM achieves up to 1.7× higher 𝐹 1 score for high-quality DNA reads and up to 19.55× higher 𝐹 1 score for DNA reads with 15% error rate, compared to state-of-the-art DNA classification tool Kraken2. Simulated at 667 MHz, EDAM provides 1, 214× average speedup over Kraken2. This makes EDAM suitable for hardware acceleration of genomic surveillance of outbreaks, such as the ongoing Covid-19 pandemic.

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“…Kaplan et.al. worked on K-means and KNN ML algorithm evaluation for processing-in-storage acceleration of ML (PRINS) [128], a system employing resistive content addressable memory (ReCAM). This architecture functions both as a storage and a massively parallel associative processor.…”

Section: B Algorithms Evaluation On Siliconmentioning

confidence: 99%

AI/ML Algorithms and Applications in VLSI Design and Technology

Amuru¹,

Vudumula²,

K.³

et al. 2022

Preprint

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An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and dataintensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

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PRINS: Processing-in-Storage Acceleration of Machine Learning

Cited by 34 publications

References 45 publications

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AI/ML Algorithms and Applications in VLSI Design and Technology

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