Printed, Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

Abstract

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm2 V−1 s−1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (Ion/Ioff ≈ 105), and a long extrapolated retention time (>107 s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high Ion/Ioff (≈104 ± 0.85), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.

Organic Semiconductor/Gold Interface Interactions: From Physisorption on Planar Surfaces to Chemical Reactions with Metal Nanoparticles

“…surface plasmon resonance) and changes in the electronic properties of NPs are observed. [6,7] For this reason, metal NPs are nowadays often merged with (organic) semiconductors to form hybrid materials that can be employed in various devices, such as solar cells, [8][9][10] light-emitting diodes, [11,12] field-effect transistors [13,14] and non-volatile memories. [15,16] Because of the technological relevance of these hybrid materials and the above-mentioned possible catalytic properties of metal NPs, which are associated with enhanced chemical reactivity, it is important to investigate the nature of the interaction between NPs and a host matrix composed of an organic semiconductor.…”

An upconverted photonic nonvolatile memory

“…Nanocrystals dispersed in the semiconductor polymer matrix as the charge-trapping element is a critical step in the quest to fabricate low-cost flash memory [35][36][37][38] . Meanwhile, using nanocrystals as charge-trapping elements can control the trapping levels and sites through solution process, which is highly desirable for printed electronics [39][40][41] . Finally, with UC nanocrystals dispersed in a three-dimensional space of the polymer matrix, we demonstrate an approach to manipulate the data storage levels with IR assistance.…”

Single‐Crystal C60 Needle/CuPc Nanoparticle Double Floating‐Gate for Low‐Voltage Organic Transistors Based Non‐Volatile Memory Devices

“…The intersection of C 60 crystals based on the highdensity N-C 60 -17 and N-C 60 -45 devices gives rise to a rapid dissipation of stored charge through the leakage channel and reduces the charge trapping ability. [ 18 ] Under these conditions, charges in the N-C 60 covered by c-PVP cannot effectively prohibit the charge transport between N-C 60 by means of the leakage path. However, the device with the isolated and uniformly distributed N-C 60 -7 crystals as the fl oating-gate exhibits the widest memory window since the discrete available trapping sites can be modulated for device miniaturization and improve the electric fi eld from the shape effect.…”

“…[ 3,5,[11][12][13] Therefore, a discrete fl oating-gate utilizing nanostructured materials rather than a conventional planar fl oating-gate can determine the size and density of charge-trapping elements in a uniform distribution for future superior high-density memory. The following possibilities have already been employed to fashion nanostructured fl oating-gate devices: [ 12,13 ] i) thermal evaporation of thin metal layers or metal islands (nanoparticles (NPs)); [ 1,[14][15][16][17][18] ii) chemisorbed or electrostatic self-assembled metal monolayers; [19][20][21][22][23][24] iii) block polymer/NP composites; [25][26][27] iv) carbon-based charge trapping materials, such as C 60 or graphene. [28][29][30][31][32][33] However, the above fl oating-gate-based memory devices generally utilize a single fl oating-gate that stores only one kind of charge (hole or electron) to signify a "1" or "0" digital state as one bit of information.…”