2017 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) 2017
DOI: 10.1109/iemcon.2017.8117242
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Priority encoder using reversible logic gates in QCA

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Cited by 7 publications
(3 citation statements)
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“…The outcome appears in Table 7. The investigation exhibits that the proposed priority encoder requires higher latency than in [48], yet the predominance is that our proposed circuit outshines the existing [40, 48] in all aspects, i.e. cell count, area, and circuit cost.…”
Section: Resultsmentioning
confidence: 96%
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“…The outcome appears in Table 7. The investigation exhibits that the proposed priority encoder requires higher latency than in [48], yet the predominance is that our proposed circuit outshines the existing [40, 48] in all aspects, i.e. cell count, area, and circuit cost.…”
Section: Resultsmentioning
confidence: 96%
“…The relationship with the recently detailed plan [40, 48] is discussed in this section. The outcome appears in Table 7.…”
Section: Resultsmentioning
confidence: 99%
“…We have categorized all the reversible gates present so far on the basis of the number of input-output vectors. [20] A⊕B B⊕C AB+BC+AC TS-3 [33] A B A⊕B⊕C RM [34] A⊕BC AB+AC AC+AB RG [35] A⊕B AB+BC+AC BC+A(B ⊕ C) RG1 [21] B AB+BC A⊕C G1 [36] B A B+AB A BC+AC+BC RG2 [21] A B ⊕C A ⊕ B A URLG [37] AB+BC+AC AB+BC+A C AB+B C+A C MPG [38] A A⊕B AB⊕C SAM [38] A AB⊕AC AC⊕AB R [34] A⊕B A C ⊕(AB) QCA1 [39] AB+BC+AC AB+BC+AC AB+BC+AC QCA2 [39] AB+BC+AC AB+BC+AC AB+BC+A C RQG [40] AB+BC+AC AB+BC+AC A⊕C Peres [41] A A⊕B AB⊕C URG [42] (A+B)⊕C B AB⊕C SSG [43] B⊕C A⊕B AB+BC+AC MNFT [44] (A⊕B)C⊕A A⊕B (A⊕B)C⊕A⊕C SRK [45] A…”
Section: Analysis Of Various Reversible Gatesmentioning
confidence: 99%