Priority-select arbiter: An efficient round-robin arbiter

Helal, Khaled A.; Attia, Sameh; Ismail, Tawfik; Mostafa, Hassan

doi:10.1109/newcas.2015.7182062

Cited by 8 publications

(5 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a future work, study soft implementation behavior when allocators and switches are harden, integrate hard router with programmable interconnects on FPGA, then compare between the two approaches and give some design recommendations. Modify the selected NoC design by using the proposed Round Robin arbiter in [20] and measure its effect on area, speed and power.…”

Section: Discussionmentioning

confidence: 99%

Design guidelines for embeded NoCs on FPGAs

Gamal

Fahmy

Ismail

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

Self Cite

View full text Add to dashboard Cite

Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-topoint interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration (PDR), reduce the compile time and improve the system performance. We compared FPGA-specific NoC components on soft and hard implementations and analyzed the efficiency gap between the two technologies to get design constraints in this space. Input module that includes memory buffers, implemented using block RAMs (BRAMs), is the module with the smallest gaps: 1.8x area, 2.9x delay and 5.3x power. Switch has the largest gap: 90x area, 7x delay and 53x power. If the router is totally hard implemented, this will save 9x area, 3.7x delay and 12x power at the expense of no flexibility (reconfigurability). By comparing our results with same flow on ASIC-specific router, we show that using FPGAspecific NoCs design improves the utility by a factor of 3x in area with a slight increase in the delay.

show abstract

Section: Discussionmentioning

confidence: 99%

Design guidelines for embeded NoCs on FPGAs

Gamal

Fahmy

Ismail

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

Self Cite

View full text Add to dashboard Cite

show abstract

“…A reasonable control network is characterized by short messages assumed. Thus, (1) The Arbiter has a Round-robin scheduling [34] approach to provide fairness in delivering requests. (2) Photonic Arbiter implements the logic for handling various path-setup messages depending on the addressing schema.…”

Section: A Network Managermentioning

confidence: 99%

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

et al. 2021

View full text Add to dashboard Cite

Photonic networks and software-defined networks are two promising technologies to improve network-onchips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the 8x8 network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.

show abstract

“…Arbiters can be categorized in terms of fairness (weak, strong or FIFO) arbiters [2,42]. In a weak fairness arbiter, every request is eventually granted.…”

Section: Conventional Arbiter Designmentioning

confidence: 99%

“…We discussed the selection of a VC from the input-port VCs in LLD and ViChaR in Chapter The VC-req is updated according to the location of the flit data in the input-port buffer. This feature of RDQ VC-Selector requires the arbitration among the input-port VCs to follow a FIFO fairness priority [42]. In FIFO fairness priority, the requesters are granted in a FIFO order of their requests.…”

Section: Fifo Arbitration and Vc Selectormentioning

confidence: 99%

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

View full text Add to dashboard Cite

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

show abstract

Priority-select arbiter: An efficient round-robin arbiter

Cited by 8 publications

References 4 publications

Design guidelines for embeded NoCs on FPGAs

Design guidelines for embeded NoCs on FPGAs

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Virtual channel organization and arbitration for network on chip router architecure

Contact Info

Product

Resources

About