Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

Abstract

We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate variables and eliminate redundant variables, which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM framework for reliability computation. We further define a susceptibility measure to identify gates whose errors are not well masked. We show that hardening a few gates can significantly improve circuit reliability.

Gate-Level Circuit Reliability Analysis: A Survey

“…An accurate analytical model for reliability analysis problem is based on the probabilistic transfer matrices (PTMs), which compute the circuit output reliability for all input patterns [10,11]. This computational framework begins with the definition of a probability matrix which is used to represent the probability of a logic gate's output for each input pattern.…”

“…Particularly, for a computer with 2 GB memory, the maximum size of the circuit that can be handled is limited to 16 input/output signals. By utilizing some advanced computation methods (such as algebraic decision diagrams (ADDs) and encoding [10,11]), the signal width may be extended up to ∼50, where the signal width is defined as the largest number of signals at any level in the circuit. Unfortunately, this limit is still computationally unacceptable in the real world for large-scale benchmark circuits (e.g., C2670 which has 157 inputs and 64 outputs).…”

“…In order to tackle this issue, a number of different approaches have been reported in literature, including probabilistic transfer matrix (PTM) method [10][11][12], Bayesian networks (BN) [13][14][15], Markov random field (MRF) [16][17][18][19][20], Monte Carlo (MC) simulation, testing-based method [3], stochastic computation model (SCM) [2,21], probabilistic gate model (PGM) [22][23][24][25], observability-based analysis [26], Boolean difference-based error calculator (BDEC), and correlation coefficient method-(CCM-) based approaches [8,[26][27][28]. In the following, we overview some of these approaches and analyze their pros and cons in terms of accuracy, efficiency, and flexibility with simulation results.…”

Reliability Study of Single Stage Multi-Input Majority Function for QCA

“…To do that the special matrices introduced in [7] for two wires swap and three wires swap, the (n x n) Identity matrix, and gate fan2 matrix showed in Figure ( …”

Modeling and Mitigating Transient Errors in Logic Circuits

“…More complex transient faults can be modeled by probability transfer matrices (PTMs) [17] which, however, require linear algebra rather than Boolean algebra for their analysis. PTMs also tend to be memory bound.…”