2019 Electron Devices Technology and Manufacturing Conference (EDTM) 2019
DOI: 10.1109/edtm.2019.8731140
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Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits

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Cited by 2 publications
(6 citation statements)
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“…The performance uniformity and the yield of the devices and circuits have been upgraded from our former work by improving the processing flow [29]. The processing started from 4H-SiC 100 mm substrates with epitaxial layers.…”
Section: Design and Fabricationmentioning
confidence: 99%
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“…The performance uniformity and the yield of the devices and circuits have been upgraded from our former work by improving the processing flow [29]. The processing started from 4H-SiC 100 mm substrates with epitaxial layers.…”
Section: Design and Fabricationmentioning
confidence: 99%
“…The mesas of the devices were etched in three reactive ion etching (RIE) steps. A high flow of SF 6 (30 sccm) was applied in the RIE to solve the photoresist re-deposition issue [29]. A sloped mesa sidewall and a uniform etching speed was achieved.…”
Section: Design and Fabricationmentioning
confidence: 99%
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“…Design of the PDK begins with the modeling and characterization of an NPN-bipolar transistor. The in-house SiC BJT low-voltage process technology optimization is described in [23]. The fabricated test structures are measured on the wafer using a hot-chuck probe-station, KEITHLEY SCS-4200 parameter analyzer, and Keysight parameter extraction and optimization software IC-CAP.…”
Section: Test-structures Ht Measurements and Modelingmentioning
confidence: 99%
“…The passivation oxide was made by plasma enhanced chemical vapor deposition (PECVD) of 100 nm SiO 2 with post-deposition annealing. More details on the SiC low power fabrication process are reported in [17,23]. The circuits have two levels of interconnects.…”
Section: Fabricationmentioning
confidence: 99%