Process-Induced Stress Effect on Reliability of ChipSeal® Passivation Technology

Abstract

It is important to take into consideration the process-induced residual stress into reliability prediction modeling. Lack of process-induced stress may lead to error in reliability prediction. Therefore, careful investigation of the stress development is critical. In this paper, the stress development induced by ChipSeal® passivation process technology has been analyzed. The ChipSeal® passivation technology has been developed to enhance the reliability of commercially-off-the-shelf plastic encaptulated microelectronics component by sealing integrated circuit at the wafer level. The analysis takes every process step into account to investigate the temperature effect on the final residual stress. The section of the fabricated structure has been modeled in two different configurations. The stress developments have been simulated by numerical method, and the results have been analyzed to identify the critical location. Three different lengths of metal layer have been considered to investigate the effect of metal layer length structure. Finally, a response surface method is employed to determine the thickness effect of individual layers and to develop design guidelines to enhance ChipSeal® reliability.