Process integration of 3D Si interposer with double-sided active chip attachments

Tzeng, Pei-Jer; Lau, John H.; Zhan, Cheng; Hsin, Yu-Chen; Chang, Phei‐Lang; Chang, Yu Han; Chen, Jui‐Chin; Wu, Chien-Ying; Lee, Ching-Kuan; Chang, Hsiang-Hung; Chien, Chun-Hsien; Lin, Chang-Hong; Ku, Tzu–Kun; Kao, Ming-Jer; Li, Ming; Cline, Julia R. K.; Saito, Keisuke; Ji, Mandy

doi:10.1109/ectc.2013.6575555

Cited by 22 publications

(6 citation statements)

References 13 publications

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“…Figure 2 shows the schematics of the double-sided interposer for 3D IC integration under consideration. Figure 3 shows the cross-section of a fully-assembly module [15]. Figure 4 shows the top-side (Left) and bottom-side (Right) of the fully assembled module [15].…”

Section: Introductionmentioning

confidence: 98%

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Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Chien

Lau

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In this investigation, the thermal and mechanical design and analysis of a TSV (through-silicon via) interposer which supports 2 active chips on its top-side and 1 active chip on its bottom-side (a real 3D IC integration with an interposer) are studied. Emphasis is placed on the thermal design and analysis of the chips' average temperatures and the applied cooling capability on the heat spreader/sink. To simplify the simulations, an equivalent model, that can preciously determine the thermal performances of TSVs and solder bumps/balls, is introduced instead of a complicate detail 3D model. Another emphasis is placed on the determination of the creep strain energy density per cycle of the solder bumps/balls between the chips and the TSV interposer, the TSV interposer and the organic package substrate, and the package substrate and the PCB (printed circuit board) under environmental thermal cycling condition.

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Section: Introductionmentioning

confidence: 98%

“…Figure 3 shows the cross-section of a fully-assembly module [15]. Figure 4 shows the top-side (Left) and bottom-side (Right) of the fully assembled module [15]. The three active dies have the same dimensions: 3.7mm x 6.5mm and the gap between the two dies on the top-side of the interposer is 1mm.…”

Section: Introductionmentioning

confidence: 99%

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Chien

Lau

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…Such high density packages can be fabricated on silicon IC using silicon dioxide or nitride dielectric layers on silicon wafers with sub-micron lithographic lines and vias by damascene or dual-damascene processes. [1][2]. Photo-sensitive dielectric materials, on the other hand, are developed for wafer level packaging to achieve below 10 m vias [3].…”

Section: Introductionmentioning

confidence: 99%

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

Suzuki¹,

Takagi

Tummala

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper describes the first demonstration of 10 m diameter interlayer vias in low-moisture uptake and low surface-roughness dry film polymer dielectric for multilayered re-distribution layer (RDL) structures to achieve 50 m bump pitch in high density organic and glass interposers. A new series of polymer dry films, ZS-100, at 10 m thickness were deposited on thin and low CTE organic or glass cores using double-sided vacuum lamination processes. The ultra-small vias were fabricated by 248nm KrF excimer laser drilling, followed by electroless and electrolytic copper plating. Fully-filled via structures were successfully fabricated without any chemical-mechanical polishing. The processes demonstrated in this paper achieve much finer bump pitch than current organic packages, and can be scaled to large panels leading to lower cost than previous work in fine pitch Si interposers using back-end of line (BEOL) wafer processes.

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“…Such ultrahigh multilayer wiring for 2.5-D interposers requires ultrasmall diameter interlayer microvias. Silicon interposers have been developed and commercialized to meet such demands using back-end-ofline processes using silicon dioxide or nitride dielectric layers with submicrometer lithographic lines and vias by damascene or dual-damascene processes [1], [2]. Silicon interposers have Y. Suzuki is with the 3D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA, and also with the Research and Develop Center, Zeon Corporation, Kawasaki 210-9507, Japan (e-mail: ysuzuki3@mail.gatech.edu).…”

Section: Introductionmentioning

confidence: 99%

Demonstration of 10-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m Microvias in Thin Dry-Film Polymer Dielectrics for High-Density Interposers

Suzuki

Furuya

Tummala

2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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This paper describes the demonstration of 10-µm diameter interlayer vias with 3.5-µm wide re-distribution layer copper wiring in a unique dry-film polymer dielectric, ZEONIF ZS100 (ZS100), suitable for panel-based high-density organic and glass interposers. The uniqueness of polymer dielectric includes low dielectric constant, low dielectric loss, low moisture uptake, and low surface roughness. The dry-film polymer dielectric was laminated on thin and low coefficient of thermal expansion organic or glass cores using double-side vacuum lamination processes. The ultrasmall microvias were drilled with 248-nm KrF excimer laser. Metallization by electroless and electrolytic copper plating successfully achieved formation of fully filled vias and copper traces simultaneously without any chemicalmechanical polishing. The processes demonstrated in this paper enable interposers with much finer bump pitch than current organic package technology. In addition, the processes can be scaled to large panels leading to lower cost than the previous work in fine pitch Si interposers fabricated through back-endof-line wafer processes.Index Terms-Excimer laser, fine pitch via, fine pitch wiring, microvia, thin dielectric film.

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Process integration of 3D Si interposer with double-sided active chip attachments

Cited by 22 publications

References 13 publications

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

Demonstration of 10-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m Microvias in Thin Dry-Film Polymer Dielectrics for High-Density Interposers

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