2013
DOI: 10.1016/j.mee.2012.08.009
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Process integration of fine pitch Cu redistribution wiring and SnCu micro-bumping for power efficient LSI devices with high-bandwidth stacked DRAM

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Cited by 3 publications
(2 citation statements)
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“…However, wafer sliding may impair the accuracy of post-bonding alignment due to thicker bumps in TLP bonding [179]. The most popular TLP material has historically been Cu-Sn owing to a low-temperature process (260 • C) and scalability [180][181][182][183]. Moreover, TLP bonding for 3D integration has utilized Au-Sn and Au-In [184][185][186].…”
Section: Metal Bondingmentioning
confidence: 99%
“…However, wafer sliding may impair the accuracy of post-bonding alignment due to thicker bumps in TLP bonding [179]. The most popular TLP material has historically been Cu-Sn owing to a low-temperature process (260 • C) and scalability [180][181][182][183]. Moreover, TLP bonding for 3D integration has utilized Au-Sn and Au-In [184][185][186].…”
Section: Metal Bondingmentioning
confidence: 99%
“…Copper plating onto PI films is a well-used process in the fabrication of the interconnections in microelectronic devices such as flexible printed circuit board (FPCB) and ultra large-scale integration (ULSI) [1][2][3]. Recently, demands for the fabrication technologies of fine Cu patterns on a PI film have increased due to the increase in demand for miniaturization and performance enhancement of electronic devices [4,5].…”
Section: Introductionmentioning
confidence: 99%