Process Optimization and Integration for Silicon Oxide Intermetal Dielectric Planarized by Chemical Mechanical Polish

Abstract

As the trend toward shrinking design rules for ultralarge scale integrated circuits (ULSI) continues, the requirements of the planarization process become more and more stringent due to concerns over narrowing lithographic process latitudes in the presence of ever-reducing depth of focus. Among the planarization technologies, chemical mechanical polishing (CMP) is the only technique that is capable of achieving global planarization across the lithographic field, and therefore becomes one of the most important ULSI process technologies for the 0.25 m generation and beyond. 1 Despite its popularity and widespread applications, the practice of CMP still remains at an empirical level owing to the numerous process parameters involved and the lack of a systematic methodology for characterizing and optimizing the process. For instance, for the planarization of intermetal dielectric (IMD) through CMP, process engineers are often confronted with the challenge of determining the thickness of deposited IMD layer that will be removed subsequently by the CMP step. This problem is further complicated when it comes to optimize the numerous CMP process parameters in order to broaden the process latitude, while maintaining a high enough planarization efficiency in the presence of varying pattern densities that would lead to over-or underpolishing of the dielectrics within a chip.To investigate the influence of each parameter over a wide range of variables and to reduce the sample size under such a complex variable experiments, this study utilized the standard L-25 orthogonal array experiments design 2,3 to derive the characteristic trends of removal rate and within-wafer nonuniformity (WIWNU) against various CMP process parameters. With the L-25 orthogonal array experimental setting, removal rate and WIWNU values may be biased if certain polishing parameters dominate the output results or there exists interaction between parameters. To correct this, parametric experiments based on the summary from orthogonal array results are performed afterward to eliminate the side effects. This also provides precise numerical data of each parameter for the decision of optimal value for subsequent experimental setting. The optimal polishing conditions derived above are then adopted to planarize the intermetal dielectric oxide films with various patterned metal pitches underneath to investigate the efficiency of planarization (%EOP). Based on the observation of the above experimental results, a rule including the integral nonuniformity, thickness of dielectric, efficiency of planarization, geometry of device, removal rate, and its variation for CMP polishing time estimation (INTEGRATE) is proposed to estimate the required dielectric thickness and polish time for the integration of IMD and CMP processes. Scanning electron microscopy (SEM) cross-sectional micrographs and chip level long scan profiles reveal the excellent global planarization achieved through the practice of the proposed INTEGRATE rule in this study. ExperimentalFirst, the plasma-e...

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“…The manufacture of semiconductor devices is significantly affected by the surface roughness of the Si wafer. Chemical mechanical planarization (CMP) is one of the key processes used for the planarization of the wafer surface [3][4][5].…”

A hybrid model combining simulation and optimization in chemical mechanical polishing process

“…They found that the carrier load, pad's modulus of elasticity, and thickness of pad would significantly affect the von Mises stress and NU, but those of the film did not have much effect. Lin et al (1999) studied systematically the chemical mechanical planarization characteristics of oxide film for optimization of intermetallic dielectric process planarization. By way of orthogonal array experimental design, the influences of physical parameters during CMP upon the polishing behaviors of silicon oxide dielectric materials were investigated.…”

Computational analysis and chemical mechanical polishing for manufacturing of optical components

“…In addition, material removal rate (MRR) which cannot be precisely predicted is another reason for generating the non-uniformity. Preston and many researchers have shown a linear relationship between MRR and pressure on the back surface of the wafer [26,31,32]. Some others have shown a nonlinear relationship between them [33,34].…”

“…Non-uniformity of the wafer surface is a primary problem. There have been experiments which show that the wafer non-uniformity decreases when down force pressure increases, slurry flow rate decreases, and the pad speed decreases [26]. However, some experiment results have shown that reducing of the pad speed increases the non-uniformity.…”

“…Effects of pressure on the non-uniformity and surface roughness have been investigated by many researchers [22,26,31,38,39,[51][52][53][54][55][56][57][58][59]. In traditional CMP, when pressure increases, MRR increases linearly, non-uniformity is slightly reduced [26,31], and the surface roughness increases [54]. The head load also causes the wafer deformation, especially when the wafer becomes thinner in ultraprecision machining [60].…”