Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application

Abstract

In order to obtain high-quality through-silicon via (TSV) arrays for high voltage applications, we optimized the fabrication processes of the Si holes, evaluated the dielectric layers, carried out hole filling by Cu plating, and detected the final structure and electric properties of the TSVs. The Si through-hole array was fabricated in an 8-inch Si substrate as follows: First, a blind Si hole array was formed by the Si deep reactive etching (DRIE) technique using the Bosch process, but with the largest width of the top scallops reduced to 540 nm and the largest notch elimidiameternated by backside grinding, which also opens the bottom ends of the Si blind holes and forms 500-μm-deep Si through holes. Then, the sidewalls of the Si holes were further smoothed by a combination of thermal oxidation and wet etching of the thermal oxide. The insulating capability of the dielectric layers was evaluated prior to metal filling by using a test kit. The metal filling of the through holes was carried out by bottom-up Cu electroplating and followed by annealing at 300 °C for 1 h to release the electroplating stress and to prevent possible large metal thermal expansion in subsequent high-temperature processes. The TSV arrays with different hole diameters and spacing were detected: no visible defects or structure peeling was found by scanning electron microscopy (SEM) observations, and no detectable interdiffusion between Cu and the dielectric layers was detected by energy dispersive X-ray (EDX) analyses. Electric tests indicated that the leakage currents between two adjacent TSVs were as low as 6.80 × 10−10 A when a DC voltage was ramped up from 0 to 350 V, and 2.86 × 10−9 A after a DC voltage was kept at 100 V for 200 s.

Research of Vertical via Based on Silicon, Ceramic and Glass

“…Liuhaodong Feng et al [ 52 ] used a combination of blind etching and back thinning instead of penetrating etching. By optimizing the deep DRIE formula and then smoothing the oxide layer by combining thermal oxidation and wet etching, the sidewall of the hole becomes very smooth: the largest scallop size is reduced to 2.13 µm in width, 540 nm in depth and 43.7% in depth, as shown in Figure 19 .…”

“…Liuhaodong Feng et al [ 52 ] studied the relationship between dielectric characteristics and the hole diameter of holes with non-smooth side walls. Figure 29 shows the dependence of 300 µm deep blind holes on dielectric characteristics without smooth side walls.…”

“… Scallops on the top side wall of the hole, with an opening of 80 μm ( a ) before optimizing DRIE parameters, the maximum width and depth of scallop were 3.41 μm and 959 nm, respectively; ( b ) the optimized DRIE parameters: the maximum width and depth of scallop are 2.13 μm and 540 nm, respectively (Reprinted with permission from Ref. [ 52 ], 2022, Feng, Liuhaodong). …”

“…( a ) Full-hole profile; ( b ) top profile; ( c ) the middle section; ( d ) bottom profile (Reprinted with permission from Ref. [ 52 ], 2022, Feng, Liuhaodong).…”

“… Leakage current test results of PECVD oxide film with a thickness of 500 nm on the substrate surface in silicon blind holes with a diameter of 50∼100 µm and a spacing of 60 μm (Reprinted with permission from Ref. [ 52 ], 2022, Feng, Liuhaodong). …”