Process options for improving electromigration performance in 32nm technology and beyond

Aubel, Oliver; Hohage, J.; Feustel, F.; Hennesthal, C.; Mayer, U.; Preuße, Axel; Nopper, Markus; Lehr, M. U.; Boemmels, J.; Wehner, Stephanie

doi:10.1109/irps.2009.5173361

Cited by 5 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…9) Due to the plasmafree process, most likely the adhesion of CuSi to SiCN is improved and therefore also the EM robustness of this interface. 10,11) This option is a very well controlled process which enables the adjustment of the required EM improvement by the gas-flux dose, yielding a certain resistance improvement (Fig. 2).…”

Section: Em Improvement Option One: Silicidationmentioning

confidence: 99%

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

Aubel

Hennesthal

Hauschildt

et al. 2011

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

This paper compares the most encouraging process options for improving electromigration performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28 nm technology nodes. In addition, the impact of the various process options on stressmigration and timedependent dielectric breakdown are discussed. #

show abstract

Section: Em Improvement Option One: Silicidationmentioning

confidence: 99%

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

Aubel

Hennesthal

Hauschildt

et al. 2011

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…The common approaches to EM improvement rely on interface engineering [1] , which usually includes either the optimization of barrier/seed processes, or the introduction of more robust interface material such as self-aligned CoWP [2] on Cu wire. The downstream EM could leverage the former method while the latter might compound the already problematic low-k dielectric TDDB reliability for the formation of metallic particle in low-k film during CoWP process.…”

Section: Introductionmentioning

confidence: 99%

Dry Etch Process Effects on Cu/low-k Dielectric Reliability for Advanced CMOS Technologies

et al. 2011

View full text Add to dashboard Cite

Cu and low-k dielectric based back-end-of-the-line (BEOL) interconnects is indispensable in advanced CMOS technologies for its significant improvement of chip resistance-capacitance (RC) delay. In this paper, we investigate the effects of dry etch process on the reliability of copper interconnects such as electromigration (EM), time dependent dielectric breakdown (TDDB) and stress migration (SM). Both the via height of its vertical part and the bevel profile of via isolation in dual damascene (DD) structure are detected to remarkably impact the final EM performance. Main contributors for TDDB include the low-k sidewall damage from ash, the interface necking right after the diluted HF (DHF) wet owing to insufficient sidewall passivation and the bowling profile from non-optimized integration process. EM enhancement related profiles are usually associated with smaller line top critical dimension (CD). This might degrade TDDB performance. We proposed the optimized etch method to address this trade-off issue. SM performance is normally defined by the mechanical and thermal properties of copper interface in DD structure. It can also be improved in etch process by post etch scheme such as N2/H2 treatment from the point view of polymer residue removal and copper interface repair.

show abstract

Process Integration of Interconnects

Balakrishnan¹,

Brain²,

Zhao³

2012

Advanced Interconnects for ULSI Technology

View full text Add to dashboard Cite

Process options for improving electromigration performance in 32nm technology and beyond

Cited by 5 publications

References 11 publications

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

Dry Etch Process Effects on Cu/low-k Dielectric Reliability for Advanced CMOS Technologies

Process Integration of Interconnects

Contact Info

Product

Resources

About