Process-variation and temperature aware soc test scheduling using particle swarm optimization

Aghaee, Nima; Peng, Zebo; Eles, Petru

doi:10.1109/idt.2011.6123092

Cited by 6 publications

(15 citation statements)

References 12 publications

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“…A solution encoding scheme is suggested in [Aghaee11b] which labels the error cells with chip clusters. The number of the decision variables grows exponentially with the number of cores and therefore the computational complexity is very high.…”

Section: Sub-tree Schedulingmentioning

confidence: 99%

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Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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Section: Sub-tree Schedulingmentioning

confidence: 99%

“…Some experiments, for chip clustering optimization for sub-trees using PSO, are reported in [Aghaee11b]. The experiments showed that the PSO performs well for this purpose.…”

Section: Sub-tree Schedulingmentioning

confidence: 99%

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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“…Efficient values for stop boosting and heating trigger temperatures for each map are found using an optimization metaheuristic similar to [2].…”

Section: mentioning

confidence: 99%

“…Additionally, power densities are considerably higher in the test mode compared to the functional mode, in particular for core-based designs [4]. The temperatures in the test mode could actually be high enough to damage the IC because of overheating [2,9,16]. This means that the application of test stimuli can raise the ICs' temperatures to their tolerable limits for large deep-submicron ICs and in particular 3D-SIC.…”

Section: Introductionmentioning

confidence: 99%

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An efficient temperature-gradient based burn-in technique for 3D stacked ICs

Aghaee¹,

Peng²,

Eles³

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Burn-in is usually carried out with high temperature and elevated voltage. Since some of the early-life failures depend not only on high temperature but also on temperature gradients, simply raising up the temperature of an IC is not sufficient to detect them. This is especially true for 3D stacked ICs, since they have usually very large temperature gradients. The efficient detection of these early-life failures requires that specific temperature gradients are enforced as a part of the burn-in process. This paper presents an efficient method to do so by applying high power stimuli to the cores of the IC under burn-in through the test access mechanism. Therefore, no external heating equipment is required. The scheduling of the heating and cooling intervals to achieve the required temperature gradients is based on thermal simulations and is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed method. I. INTRODUCTIONBurn-in is a common way of accelerating and detecting early-life failures, and should be done with low cost in a reasonably short time. For this purpose, usually the dies are operated at elevated temperature and voltage. The elevated temperature and voltage speed up the aging and wear mechanisms so that the dies experience their early life before testing. The wear mechanisms that are speeded up include metal stress voiding and electromigration, metal slivers bridging shorts, as well as gate-oxide wear-out and breakdown [11].Recently several studies have, however, shown that some wear mechanisms are speeded up more efficiently by large temperature gradient rather than the high temperature itself. A temperaturegradient induced wear mechanism is identified in [12] which shows that a metal layer elevation happens rapidly at the points on the die that are experiencing a large temperature gradient. Moreover, in the atomic flux equation, used to model electromigration, temperature gradient is present directly and also indirectly through its effect on the mechanical-stress gradient [10]. Therefore, a burn-in process that has not created the appropriate thermal scenarios do not sufficiently speed up the formation of the defects that depend on large temperature gradients and consequently such early-life defects will go undetected. In order to prevent these test escapes, it is necessary to introduce a burn-in process that enforces appropriate temperature scenarios on the IC. This necessity is more urgent for the ICs that suffer from large temperature gradients, such as 3D-Stacked ICs (3D-SIC), which have considerably larger temperature gradients compared with 2D ICs (three times is reported in [13]). Moreover, 3D-SIC technology is one of the most promising future technologies [8]. Therefore, in this paper we focus on 3D-SICs. 3D-SIC technology, similar to other deep submicron technologies, suffers from high power densities. Additionally, power densities are considerably higher in the test mode compared to the functional mode, in parti...

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Process-Variation and Temperature Aware SoC Test Scheduling Technique

2013

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High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoCs). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.

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Process-variation and temperature aware soc test scheduling using particle swarm optimization

Cited by 6 publications

References 12 publications

Thermal Issues in Testing of Advanced Systems on Chip

Thermal Issues in Testing of Advanced Systems on Chip

An efficient temperature-gradient based burn-in technique for 3D stacked ICs

Process-Variation and Temperature Aware SoC Test Scheduling Technique

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