Process variation aware clock tree routing

Liu, Bing; Hu, Jinglu; Ellis, Gary; Su, Haihua

doi:10.1145/640033.640037

Cited by 9 publications

(23 citation statements)

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“…But, in real LSI designs, tree clock network is usually used and therefore methods of reducing the clock skew fluctuations for tree clock structures are desired. References [3] and [4] proposed clock tree routing methods for minimizing clock skew within a chip considering interconnect process variations.…”

Section: Introductionmentioning

confidence: 99%

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

Kobayashi¹,

Minami²

2013

IEICE Trans. Inf. & Syst.

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SUMMARYAs the LSI process technology advances and the gate size becomes smaller, the signal delay on interconnect becomes a significant factor in the signal path delay. Also, as the size of interconnect structure becomes smaller, the interconnect process variations have become one of the dominant factors which influence the signal delay and thus clock skew. Therefore, controlling the influence of interconnect process variations on clock skew is a crucial issue in the advanced process technologies. In this paper, we propose a method for minimizing clock skew fluctuations caused by interconnect process variations. The proposed method identifies the suitable balance of clock buffer size and wire length in order to minimize the clock skew fluctuations caused by the interconnect process variations. Experimental results on test circuits of 28 nm process technology show that the proposed method reduces the clock skew fluctuations by 30-92% compared to the conventional method.

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Section: Introductionmentioning

confidence: 99%

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

Kobayashi¹,

Minami²

2013

IEICE Trans. Inf. & Syst.

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“…Lu, et al, presented an approach [8] called MinSV (Minimal Skew Violations) to construct process variation tolerant clock trees that aligns the center of the skew range at the center of the permissible range for critical sink pairs. The worstcase skew due to process variations is used to guide the layout embedding to achieve this alignment.…”

Section: Introductionmentioning

confidence: 99%

“…The main contribution of this paper is to propose a probabilistic method that minimizes the number of skew violations given a set of skew permissible ranges for sink pairs. To illustrate, first, we propose a statistical-centering approach in contrast to the corner-point approach in [8]. The moments of the skew distribution are employed to choose the ideal center measure among the mean, median and mode.…”

Section: Introductionmentioning

confidence: 99%

“…Our work includes a new delay computation mechanism that incorporates fitted Elmore delay model [11] with analysis of variance (ANOVA) [12] and principle component analysis (PCA) to take into consideration correlations among width and thickness geometric parameters, reduce the number of uncertainties and thus simplify the delay formulation. Second, to avoid a sub-optimal design and excessive violations due to one single critical pair comparison [8], we follow the all pair critical pair comparison idea presented in [9] [10] and impose a weight function based upon both path criticality and permissible range criticality that assigns appropriate importance to every sink pair. Finally, the current paper discusses a topology generation algorithm which takes the width and thickness variation trend into account.…”

Section: Introductionmentioning

confidence: 99%

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Statistical clock tree routing for robustness to process variations

Padmanabhan

Wang

2006

Proceedings of the 2006 International Symposium on Physical Design

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Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high speed, large area clock networks. To achieve multi-GHz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. We propose a statistical centering based clock routing algorithm built upon DME that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by: i) choosing the best center measure which is dynamically based on the first three moments of the skew distribution, and ii) designing for all sink pairs in the subtrees simultaneously. In addition, a variation aware abstract topology generation algorithm is proposed in this paper.Experiments on benchmark circuits demonstrate the efficiency of the proposed method in reducing the number of skew violations by 12% − 37%.

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“…During the design phase, clock skew can arise due to unbalanced clock path delays resulting from unexpected changes in the capacitive loading at the clock sinks and routing constraints. To address this, extensive work has been performed on automatic sizing and routing of clock trees to minimize skew during design time [1][2] [3]. However, even if clock skew constraints are met at design time, process variations can introduce unwanted clock skew during the fabrication of the chip, thereby compromising the obtainable performance.…”

Section: Introductionmentioning

confidence: 99%