Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs

Abstract

As technology scales, the impact of process variation on the maximum supported frequency (FMAX) of individual cores in a multiprocessor system-on-chip (MPSoC) becomes more pronounced. Task allocation without variation-aware performance analysis can greatly compromise performance and lead to a significant loss in yield, defined as the percentage of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for best-effort and real-time streaming applications modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications.The four main contributions of this work are (1) distinguishing best-effort firm real-time and soft real-time application classes, which require different optimization criteria, (2) using dataflow graphs, which are well suited for modeling and analysis of streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding, (3) we present two optimization approaches, which give different improvement results at different costs, (4) we present both exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of seven real applications and are compared to mapping methods that are unaware of hardware variation. Our results demonstrate (1) improvements in the average performance (3% on average) for best-effort applications, and (2) for firm real-time and soft real-time applications, yield improvements of up to 27% with an average of 15%, showing the effectiveness of our approaches.

Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation

“…To determine the throughput requirement, each application is mapped to the platform with the specified target frequencies such that the throughput is maximized. The heuristic mapping algorithm presented in Mirzoyan et al [2014] is used for finding a mapping with maximized throughput. The result of the mapping is a throughput value, which is taken as the requirement for each application.…”

Task Assignment Algorithms for Multicore Platforms with Process Variations

“…Existing works of Teodorescu et al [14], Stamoulis et al [15] consider the heterogeneity in the die due to process variations and try to maximize the performance of the given set of workloads. There are many reported works that address variation aware task mapping [16][17][18] that tries to take into account the communication requirements between the tasks while trying to maximize the performance. Ding et al's work [19] talks about adaptive application execution i.e assigning threads of an application to the cores of a chip multiprocessor with process variation using thread mapping schemes that can potentially exploit the existing heterogeneity in power and performance characteristics of the cores to optimize performance, energy consumption and energy-delay product.…”

Yield‐driven design‐time task scheduling techniques for multi‐processor system on chips under process variation: a comparative study

“…This section tries to provide a brief overview of VAREX for being self-contained, yet the readers can refer to [13,14] for more details. Gaussian frequency distribution Singhal [3] performance yield SPDAG 2 NA, timing yields of cores are given Mirzoyan [4] performance yield SDFG 3 Discretised Gaussian frequency distribution Metaheuristic-based Algorithms Chon [5] performance yield DAG Discretised Gaussian frequency distribution Huang [6] performance yield DAG VARIUS [12], An approximative model to propagate variability in L eff and V th to the frequency of cores Momtazpour [7] power yield, performance yield wDAG Gaussian frequency distribution Momtazpour [8] power yield, performance yield wDAG an approximative model to propagate variability in L eff , V th and T ox to the frequency of cores ILP-based Algorithms Singhal [9] throughput, performance yield DAG NA, timing yields of cores are given Bhardwaj [10] power-performance yield DAG Gaussian frequency distribution Ghorbani [11] power yield, performance yield wDAG Gaussian frequency distribution 1 Weighted directed acyclic graph.…”

“…As stated in the previous section, most of the variation models used previously at MPSoC‐level either assume simple Gaussian distribution for frequency of cores [2, 4, 5, 7, 10, 11] or use approximative models to propagate the variations in transistor‐level parameters to system‐level components [6, 8]. For example, in VARIUS [12], the variation model assumes uniform distribution of identical critical paths across die, where each of the critical paths contains similar number of identical FO4 Inverter.…”

“…As another work, Singhal et al [3] introduced a dynamic programming‐based variation‐aware task scheduling and configuration selection algorithm, that is limited to applications with only series or parallel task graphs. Recently, Mirzoyan et al [4] developed some heuristic variation‐aware task scheduling methods that are limited to real‐time streaming applications with synchronous data flow graph (SDFG) model.…”