Process Variation-Aware Vdd Assignment Technique for Repeated Interconnects

Abstract

Variation during the die manufacturing process is an increasing concern as we move further along the technology roadmap. Designers are looking to improve their designs by making their circuits tolerant to these variations while incurring in as little overhead as possible. A supply voltage (Vdd) assignment technique is proposed to correct the effects of intra-die channel length variation (Leff) on delay, and consequently, on power in 70nm CMOS. By using the proposed Vdd assignment technique on a one-bit repeated interconnect, the delay spread is reduced by 90%, with a negligible power overhead of only 0.74%.