Process variation impacts on optical overlay accuracy signature

Dirawi, Rawi; Katz, Shlomit; Volkovich, Roie

doi:10.1117/12.2583616

Cited by 4 publications

(4 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The differential signal obtained using scatterometry overlay follows the function of illuminated wavelength and the layer/optical path difference which can introduce error/noise. To lower the metrology accuracy error, multi-pixel-based merits can be used for validating acquisition quality in a pixel overlay perspective [5].…”

Section: Methodology 21 Scol Accuracy Meritsmentioning

confidence: 99%

ADI to in-cell overlay stability improvement for DRAM using novel scatterometry and comprehensive process control

Kim

Jeong

et al. 2023

Metrology, Inspection, and Process Control XXXVII

View full text Add to dashboard Cite

As the cell size of memory devices continues to shrink, tighter on-product overlay (OPO) specs require more accurate and robust overlay control. The overlay error budget mainly consists of the reticle, scanner, process, and metrology errors. The metrology budget is generally required to be <10% of the OPO control budget so that the accuracy and robustness of overlay metrology become more crucial as pattern size gets smaller on current 1x nm DRAM nodes. For overlay control in high-volume manufacturing (HVM), the primary optical overlay metrology typically used is Image-Based Overlay (IBO). In many cases, scatterometry overlay (SCOL), using a direct grating-scanning method, was shown to achieve more accurate After Development Inspection (ADI) overlay measurements. Using a tunable source and customized illumination pupil to directly scan within the grating cell, this technology improves accuracy by reducing the contribution of pattern surroundings in the scribe line, resulting in improved OPO control stability. Since the purpose of overlay control is to minimize actual device pattern misregistration, as measured after the etching process (AEI), achieving accurate and stable characterization of the systematic deviation between ADI and AEI overlay known as Non-Zero-Offset (NZO) is critically important. Accurate NZO applied to the scanner via the Advanced-Process-Control (APC) loop enables effective scanner overlay control at the post-lithography ADI step. This paper demonstrates a new scatterometry overlay technology adopted in DRAM use cases that resulted in OPO and NZO stability improvement. In addition, we demonstrate an efficient method to monitor HVM run-to-run overlay performance and NZO stability by comprehensive dataset modeling combining ADI and AEI.

show abstract

Section: Methodology 21 Scol Accuracy Meritsmentioning

confidence: 99%

ADI to in-cell overlay stability improvement for DRAM using novel scatterometry and comprehensive process control

Kim

Jeong

et al. 2023

Metrology, Inspection, and Process Control XXXVII

View full text Add to dashboard Cite

show abstract

“…Large Pupil 3S represents inaccuracy and indicates inaccurate regions of landscapes that are called resonant areas on the SCOL landscape . [3] A smaller Pupil 3S is the right direction on SCOL metrology to minimize measurement noise. Although a small Pupil 3S does not guarantee accuracy all the time, it could result in better Non-Zero Offset (NZO) and stable measurability on multiple lots of DRAM layers in HVM in certain cases.…”

Section: Scol Accuracy Meritsmentioning

confidence: 99%

SCOL long wavelength measurements on DRAM thick layers

Lee,

Lee

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

View full text Add to dashboard Cite

As the semiconductor industry rapidly approaches lithography nodes beyond 3nm, On Product Overlay (OPO) becomes a critical factor in enabling process control and manufacturing yield. The correspondingly tight OPO error budget emphasizes the importance of accurate overlay (OVL) metrology for capturing and tracking ever-smaller processes and patterning variations. In the DRAM memory segment, additional challenges arise in layers around the storage node, where the critical patterning steps are on thick layers with denser patterns than on other layers.A major challenge for optical overlay measurement on storage node layers comes from opaque optical stack materials whose optical properties reduce signal penetration effectiveness. Another key challenge is the high aspect ratio between the stack height and the target pitch, reducing diffraction efficiency and sensitivity. IBO (Image-Based Overlay) studies have shown that long wavelength (WL) improves the measurability of thick layers and significantly improves overlay results. In this paper, it is reported that longer WL (>800nm) can overcome the measurability challenges and achieve accurate results on a DRAM storage node layer. We present how improvements in raw overlay signal (pupil-plane image uniformity) further result in Total Measurement Uncertainty (TMU) and residual improvements over previous baseline solutions. Long WL enables DRAM manufacturers to meet and tighten OPO specifications on thick, storage node layers in their advanced technology architectures.

show abstract

“…Accuracy refers to the closeness of the measurements to the true values. Some of these challenges and solution details are in previous works [5,6].…”

Section: Introductionmentioning

confidence: 99%

Advanced processing control for wafer-to-wafer hybrid bonding

Aditya Kumar Roy,

Housley,

Engelhard

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

View full text Add to dashboard Cite

3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs.The 3D heterogeneous integration roadmap shows a decrease in the bonding bumps/pads pitch to a submicrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the waferto-wafer (W2W) bonding process to reduce interconnect pitch to small values. In the W2W process, a wafer bonder is used to align and bond two whole wafers. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to ensure the copper pads line up properly before being bonded, driving an increased need for overlay metrology precision and die-bonder control. The bonded wafers are subsequently cut up into stacked chips using a dicing process and then undergo testing and further packaging.Advanced processing control (APC) for W2W hybrid bonding is an important factor in fulfilling the target onproduct overlay (OPO) via litho inputs, in-plane distortion (IPD), overlay (OVL) and bonder correction knobs. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget.

show abstract

Process variation impacts on optical overlay accuracy signature

Cited by 4 publications

References 0 publications

ADI to in-cell overlay stability improvement for DRAM using novel scatterometry and comprehensive process control

ADI to in-cell overlay stability improvement for DRAM using novel scatterometry and comprehensive process control

SCOL long wavelength measurements on DRAM thick layers

Advanced processing control for wafer-to-wafer hybrid bonding

Contact Info

Product

Resources

About