2020
DOI: 10.1007/978-3-030-44907-0_9
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Processing Systems for Deep Learning Inference on Edge Devices

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Cited by 9 publications
(3 citation statements)
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References 26 publications
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“…The performance variation is a strong selection criterion as it depends on the technology, data size and area efficiency of the AI/ML design. These different features justify the differences in peak performance among the architectures [95]. Several vendors involved with the design of AI/ML ASIC-based accelerators have selected their own hardware architecture.…”
Section: Asic-based Acceleratorsmentioning
confidence: 99%
“…The performance variation is a strong selection criterion as it depends on the technology, data size and area efficiency of the AI/ML design. These different features justify the differences in peak performance among the architectures [95]. Several vendors involved with the design of AI/ML ASIC-based accelerators have selected their own hardware architecture.…”
Section: Asic-based Acceleratorsmentioning
confidence: 99%
“…CNNs in particular have very deep and computationally intensive architectures, but the operations involved are highly modular and repetitive, making them excellent candidates for acceleration through custom hardware. A survey by Véstias et al [49] focuses specifically on accelerating CNNs using reconfigurable computing hardware, while another from Véstias [50] focuses on hardware acceleration of deep learning in general.…”
Section: B Enabling Ai In the Edgementioning
confidence: 99%
“…Computing platforms for deep learning on edge cannot rely on high-performance devices since they either have high energy consumption or low power efficiency and are relatively expensive [11]. Embedded processors are used in many low cost devices but achieve only a few dozen GFLOPs (Giga FLoating-point Operations Per second) with low power efficiency, insufficient for real or almost realtime processing of CNNs.…”
Section: Related Workmentioning
confidence: 99%