Processor Aware Anticipatory Prefetching in Loops

Kalogeropulos, S.; Rajagopalan, Mohan; Rao, V.; Song, Yonghong; Tirumalai, P.

doi:10.1109/hpca.2004.10029

Cited by 5 publications

(8 citation statements)

References 21 publications

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“…Figure 2 shows the overall algorithm. In Figure 2(a), a loop hierarchy tree is first built for the whole program, followed by reuse analysis and prefetch candidate identification [7] to introduce only necessary prefetches and avoid issuing redundant ones. The function prefetching using helper thread driver is then called recursively to identify candidates and generate codes for helper threading.…”

Section: Overviewmentioning

confidence: 99%

“…These prefetches can bring data to the shared L2 cache, representing a potentially significant execution time saving for the main thread. The above load or store is called an effective prefetch candidate, if its address computation depends on at least another load in the same loop body or the load/store is identified as a prefetch candidate by using reuse analysis [7].…”

Section: Selecting Candidate Loopsmentioning

confidence: 99%

“…Currently, prefetching is most effective for memory access streams where future memory addresses can be easily predicted using loop index values [7,18,19]. For such access streams, software prefetch instructions are inserted into the program to bring data into cache before the use.…”

Section: Introductionmentioning

confidence: 99%

“…Although it is quite successful for many cases [7,19], interleaved prefetching tends to be less effective for two kinds of codes. First, for codes with complex array subscripts, memory access strides are often loop variant, even predictable, at compile time.…”

Section: Introductionmentioning

confidence: 99%

“…The complexity and overhead increase if the subscript evaluation involves loads that themselves must be prefetched and made speculative. One such example is an indexed array access [7]. If the prefetched data is already in the cache, such large overheads can cause a significant slowdown.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Design and implementation of a compiler framework for helper threading on multi-core processors

Song

Kalogeropulos

Tirumalai

2005

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)

Self Cite

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Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes in parallel with the main thread that it attempts to accelerate. In this paper, the helper thread merely prefetches data into a shared cache and does not incur any other programmer visible effects. Helper thread prefetching has been proposed as a viable solution in various scenarios where it is difficult to prefetch efficiently within the main thread itself. This paper presents our helper threading experience on SUN's second dual-core SPARC microprocessor, the UltraSPARC IV+. The two cores on this processor share an on-chip L2 and an off-chip L3 cache. We present a compiler framework to automatically construct helper threads and evaluate our scheme on the UltraSPARC IV+ processor. Our preliminary results using helper threads on the SPEC CPU2000 suite show gains of up to 22% on programs that suffer substantial L2 cache misses while at the same time incurring negligible losses on programs that do not suffer L2 cache misses.

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Section: Overviewmentioning

confidence: 99%

Section: Selecting Candidate Loopsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design and implementation of a compiler framework for helper threading on multi-core processors

Song

Kalogeropulos

Tirumalai

2005

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)

Self Cite

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Parallel test tasks scheduling on multi-core platform

Wang

Fang

Cheng-jin

2008

2008 Ieee Autotestcon

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Aimed at the problem that traditional test program couldn't effectively enhance the test efficiency, three decompose method which based on mission, data and data stream were brought forward to solve the test problem of parallel decompose. Multi-core technology was imported in parallel test platform to make the real time ability of the parallel mission improved. In order to work out the issue that test program based on single-core couldn't utilize MCP technology effectively, schedule strategy of parallel test mission is advanced to optimize test flow and mission schedule. According to the result of experimentation, performance of plat based on MCP enhanced 30%~50% against single-core plat.

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Effective stream-based and execution-based data prefetching

Iacobovici

Spracklen

Kadambi

et al. 2004

Proceedings of the 18th Annual International Conference on Supercomputing

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With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response to this continuing trend, most modern processors now support hardware (HW) prefetchers, which act to reduce the missing loads observed by an application.This paper analyzes the behavior of cache-missing loads in SPEC CPU2000 and highlights the inability of unit and single non-unit stride prefetchers to correctly prefetch for some commonly occurring streams. In response to this analysis, a novel multi-stride prefetcher, that supports streams with up to four distinct strides, is proposed. Performance analysis for SPEC CPU2000 illustrates that the proposed multistride prefetcher can outperform current stride prefetchers on several benchmarks; most notably on mcf, lucas and facerec, where it achieves an additional performance gain of up to 57%. Performance of the strided HW prefetchers is also contrasted with another recently proposed prefetch scheme, runahead execution (RAE), and the synergy between the schemes is investigated.

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Processor Aware Anticipatory Prefetching in Loops

Cited by 5 publications

References 21 publications

Design and implementation of a compiler framework for helper threading on multi-core processors

Design and implementation of a compiler framework for helper threading on multi-core processors

Parallel test tasks scheduling on multi-core platform

Effective stream-based and execution-based data prefetching

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