Processor-in-the-Loop implementation of an Adjusting Space Vector Pulse Width Modulation for Suppressing Zero-Sequence Circulating Current in Parallel PWM converters

Abstract

Grid-connected common DC-bus parallel three-phase PWM converters system is widely used in many power systems due to its advantages, including high reliability, sinusoidal grid currents, lower switching frequency, stable DC-bus voltage, and good flexibility. However, this topology suffers from zero-sequence-circulating-current (ZSCC), which will deteriorate the control performance, distort the grid currents, and increase power losses. In this context, an adjusted space vector pulse width modulation strategy (ASVPWM) based on ZSCC fuzzy logic control loop (ZSCC-FLC) is proposed not only to suppress the ZSCC but also to mitigate its ripples and grid current harmonics, especially the third harmonic and their multiples. The main objective of the proposed ZSCC-FLC based ASVPWM strategy is to enforce the ZSCC to zero with very lower ripples in order to accurately provide the appropriate adjusting variable for the duty rations of zero state vectors of ASVPWM. A processor-in-the-loop (PIL) co-simulation is implemented using embedded hardware on the STM32F407 microcontroller discovery-development-board as an experimental study of the proposed ZSCC-FLC based ASVPWM strategy for parallel three-phase PWM converters under balanced and unbalanced grid voltage. Finally, we quantitatively compare both the proposed ZSCC-FLC based ASVPWM strategy to the ZSCC-PIC. This comparison verifies the superiority and effectiveness of the proposed strategy over the ZSCC-PIC strategy in terms of ZSCC, ripples, and inputs currents harmonics.