Producing Random Bits with Delay-Line-Based Ring Oscillators

Jessa, M.; Matuszewski, Łukasz

doi:10.2478/eletel-2013-0005

Cited by 5 publications

(8 citation statements)

References 44 publications

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“…Moreover, propagation delays in all circuit paths and gates vary in time, because of shot noise, thermal noise and supply voltage instability [28], [41]. Taking into account these factors the more realistic formula for fH is the following [28], [39]:…”

Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

“…We can choose an even number of inverters, a chain of laches or delay lines available in FPGAs. The comparison of nominal frequencies of ROs using different types of delays is available in [39]. In this article, the chain of latches was used as τ.…”

Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

“…Parameter dik is the delay of the k-th interconnections in ring oscillator, Δdtk is the variation of the delay in the k-th component and interconnection caused by variation of temperature, Δdvk represents the variation of the delay in the k-th component and interconnection caused by supply voltage instability and Δdrk define others random delays in the k-th element and path in the ring oscillator, e.g., transition spacing or crosstalk's. The accumulated jitter can be divided into deterministic component and nondeterministic one [28], [39]:…”

Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

“…The ring oscillators must also have significantly different nominal frequencies to prevent the injection attack [40]. It forces to use delay lines built into FPGAs instead of inverters or latches [39]. …”

mentioning

confidence: 99%

“…To obtain unbiased sequence that pass all known statistical tests for random sequences, e.g. NIST 800-22 test suite, Diehard, TestU01 or UC1, we need to combine bit streams produced by many RObased random bit generators [34]- [39]. The ring oscillators must also have significantly different nominal frequencies to prevent the injection attack [40].…”

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confidence: 99%

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A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Łoza¹,

Matuszewski²,

Jessa³

2015

International Journal of Electronics and Telecommunications

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Abstract-Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components -the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies. analog random number generator in one microchip in order to be used in encryption/decryption process in dedicated solutions. Most of cryptographic systems are digital constructions. Therefore, it is expected that random number generators should be purely digital constructions, simply integrated in one chip. Nowadays there is a trend to find in digital circuits some behaviors or methods that will give possibility to produce random bit sequences "on demand", with high bit rate, without any possibility to having access to elements of these sequences. It is proposed to use generators with jitter, constructed by using reprogrammable digital circuits or constructions based on meta-stability [31], [32]. Because the latter phenomenon, although interesting, is rather impractical for producing random bits in contemporary FPGAs [33], the most significant are concepts using ring oscillators or Galois Ring Oscillators (GARO). In both approaches jitter is used for signal generation [27], [31]. Random bit sequence is obtained by sampling signal generated by RO or GARO with rectangular wave with lower frequency. To obtain unbiased sequence that pass all known statistical tests for random sequences, e.g. NIST 800-22 test suite, Diehard, TestU01 or UC1, we need to combine bit streams produced by many RObased random bit generators [34]- [39]. The ring oscillators must also have significantly different nominal frequencies to prevent the injection attack [40]. It forces to use delay lines built into FPGAs instead of inverters or latches [39]. KeywordsTo decrease the number of RO-based random bit generators necessary to pass all statistical tests, it is proposed in this paper to use SHA-256 hash function as post-processing. Both elements -RBG and SHA-256, were implemented in the same Virtex 5 FPGA (XL5VLX50T). Through experiments it has been shown that the minimal number of ROs that should be used for building a random ...

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Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Łoza¹,

Matuszewski²,

Jessa³

2015

International Journal of Electronics and Telecommunications

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Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

Yeniceri

Yalçın

2015

Circuit Theory & Apps

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Summary In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look‐up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low‐pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field‐programmable gate array and utilized in a true random bit generator. Copyright © 2015 John Wiley & Sons, Ltd.

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An efficient post-processing method for pipelined pseudo-random number generator in SoC-FPGA

Dąbal

Pełka

2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.

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Producing Random Bits with Delay-Line-Based Ring Oscillators

Cited by 5 publications

References 44 publications

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

An efficient post-processing method for pipelined pseudo-random number generator in SoC-FPGA

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