Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

Abstract

In this paper we introduce an approach to increase density of field-effect transistors framework a two-level current-mode logic gate in latch. Framework the approach we consider manufacturing the logic gate in heterostructure with specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress.