Program/erase injection current characteristics of a low-voltage low-power NROM using high-K materials as the tunnel dielectric

Abstract

The program and erase injection current characteristics of a NROM with SiO 2 , HfO 2 , LaAlO 3 and Al 2 O 3 as the tunnel dielectric, respectively, are studied in this paper. Due to the lower electron and hole energy barriers introduced by LaAlO 3 , both the program and erase injection current densities of the NROM using LaAlO 3 as the tunnel dielectric are increased dramatically. The injection efficiency is also improved significantly, which indicates that the introduction of LaAlO 3 can lower the operation voltage of NROM cells. We show that the bit line voltage can be reduced to 3 V for both program and erase operations of NROM cells with LaAlO 3 of 5 nm and 8 nm equivalent oxide thickness (EOT). This can greatly reduce the additional circuits to generate high voltages in a nonvolatile memory chip, meanwhile maintaining sufficient program/erase (P/E) performance and reliability. Our study also shows that the drain disturb is alleviated during programming and erasing the NROM cell with the LaAlO 3 tunnel dielectric due to the lower operating voltages (V BL = 3 V). Hence a low-voltage low-power NROM flash memory device operation can be achieved by using LaAlO 3 as the tunnel dielectric, due to the enhancement of the P/E injection current.

Direct tunneling through high-κ amorphous HfO2: Effects of chemical modification

“…[5][6][7][8] For high-κ dielectric HfO 2 , the barrier height is 1.5 eV for electrons and 3.4eV for holes, to be compared to 3.1eV and 4.9eV of SiO 2 . 9 Knowing the thickness and the potential height of an ideal smooth tunnel barrier, calculating electron transmission coefficient is a textbook problem of quantum mechanics. 10 For somewhat more complicated barriers, approximations such as the Wentzel-Kramers-Brillouin (WKB) approximation are widely applied, resulting to such well-known formula as the Fowler-Nordheim law.…”

A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure

“…The injection current density from the gate is much larger in the recessed channel cells due to both effective capacitance coupling and electric field enhancement in the tunnel layer as mentioned above, which indicates that the recessed channel cell can have faster programming speed at the same gate bias compared with the planar cell. For the reasonable programming time of several hundred microseconds, the average injection current density should be more than 10 −9 A µm −2 [14]. Thus, the minimum programming voltage, which is given in figure 6, can be obtained from figure 5 according to the requirement of the injection current density.…”

A control-gate-assisted erasing method for a single-poly EEPROM cell with metallic control gate structure

“…Recently, low cost has been an important consideration in nonvolatile memory (NVM) application. In addition, the demands of the embedded nonvolatile memory for system integration on a chip is rapidly increasing, Among the various NVM memory structures [1][2][3][4][5][6], single-poly memory is one of the promising solutions for low-cost-embedded NVM applications [6][7][8][9][10][11][12]. The conventional single-poly EEPROM cells with diffused n-well CG suffer some issues, such as the large CG junction capacitance and resistance, the reduction of the coupling factor (α CG ), and the signal disturbance from n-well CG to the adjacent blocks through the substrate [11,12], as well as the slow erasing speed.…”