Programming the Intel 80-core network-on-a-chip Terascale Processor

Mattson, Timothy G.; Wijngaart, Rob Van der; Frumkin, Michael

doi:10.1109/sc.2008.5213921

Cited by 52 publications

(38 citation statements)

References 4 publications

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“…One way to scale the number of cores is to utilize Non-Coherent Cache (NCC) architectures that skip implementing cache coherence in hardware. While NCC architectures are power-efficient and scalable, it is difficult to program them [20]. on-and off-chip shared memory yet fail to take into account parallel systems.…”

Section: List Of Tablesmentioning

confidence: 99%

Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures

Rawat¹,

Shrivastava²

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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As the number of cores per chip increases, maintaining cache coherence becomes prohibitive for both power and performance. Non Coherent Cache (NCC) architectures do away with hardware-based cache coherence, but they become difficult to program.Some existing architectures provide a middle ground by providing some shared memory in the hardware. Specifically, the 48-core Intel Single-chip Cloud Computer (SCC) provides some off-chip (DRAM) shared memory and some on-chip (SRAM) shared memory. We call such architectures Hybrid Shared Memory, or HSM, manycore architectures. However, how to efficiently execute multi-threaded programs on HSMarchitectures is an open problem. To be able to execute a multi-threaded program correctly on HSM architectures, the compiler must: i) identify all the shared data and map it to the shared memory, and ii) map the frequently accessed shared data to the on-chip shared memory. This work presents a source-to-source translator written using CETUS [7] that identifies a conservative superset of all the shared data in a multi-threaded application and maps it to the off-chip shared memory such that it enables execution on HSM architectures. This improves the performance of our benchmarks by 32x. Following, we identify and map the frequently accessed shared data to the on-chip shared memory. This further improves the performance of our benchmarks by 8x on average.

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Section: List Of Tablesmentioning

confidence: 99%

Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures

Rawat¹,

Shrivastava²

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…Some other important concepts in NOC are topology, routing, flow control, buffer management, quality of service and network interfaces and they have been studied in acclaimed proposals such as Aetherial [9], Nostrum [10], Xpipes [11], Intel 80 Core NOC [12], and Mango [13]. They all make different design decisions, to achieve their design goals.…”

Section: B Network-on-chipmentioning

confidence: 99%

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

Karadeniz

Mhamdi

Goossens

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Abstract-Network routers rely on an important hardware component, namely the switch fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A switch fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding.In this paper, we revisit our previously proposed Networkon-Chip (NOC) based switch fabric architecture and: 1) propose an FPGA based hardware implementation of the NOC switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.

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“…Intel's 80-core Terascale Processor [10] was the first generally programmable microprocessor to break the teraflop barrier. It has a good flop/Watt ratio, making it an interesting candidate for future correlators.…”

Section: Related Workmentioning

confidence: 99%

Using many-core hardware to correlate radio astronomy signals

Nieuwpoort

Romein

2009

Proceedings of the 23rd International Conference on Supercomputing

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A recent development in radio astronomy is to replace traditional dishes with many small antennas. The signals are combined to form one large, virtual telescope. The enormous data streams are crosscorrelated to filter out noise. This is especially challenging, since the computational demands grow quadratically with the number of data streams. Moreover, the correlator is not only computationally intensive, but also very I/O intensive. The LOFAR telescope, for instance, will produce over 100 terabytes per day. The future SKA telescope will even require in the order of exaflops, and petabits/s of I/O. A recent trend is to correlate in software instead of dedicated hardware. This is done to increase flexibility and to reduce development efforts. Examples include e-VLBI and LOFAR.In this paper, we evaluate the correlator algorithm on multi-core CPUs and many-core architectures, such as NVIDIA and ATI GPUs, and the Cell/B.E. The correlator is a streaming, real-time application, and is much more I/O intensive than applications that are typically implemented on many-core hardware today. We compare with the LOFAR production correlator on an IBM Blue Gene/P supercomputer. We investigate performance, power efficiency, and programmability. We identify several important architectural problems which cause architectures to perform suboptimally. Our findings are applicable to data-intensive applications in general.The results show that the processing power and memory bandwidth of current GPUs are highly imbalanced for correlation purposes. While the production correlator on the Blue Gene/P achieves a superb 96% of the theoretical peak performance, this is only 14% on ATI GPUs, and 26% on NVIDIA GPUs. The Cell/B.E. processor, in contrast, achieves an excellent 92%. We found that the Cell/B.E. is also the most energy-efficient solution, it runs the correlator 5-7 times more energy efficiently than the Blue Gene/P. The research presented is an important pathfinder for next-generation telescopes.

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Programming the Intel 80-core network-on-a-chip Terascale Processor

Cited by 52 publications

References 4 publications

Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures

Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

Using many-core hardware to correlate radio astronomy signals

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