Progress in a novel architecture for high performance processing

Zhang, Zhiwei; Li, Meng; Liu, Zijun; Du, Xiaoyong; Xie, Shijie; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin

doi:10.7567/jjap.57.04fa03

Cited by 2 publications

(2 citation statements)

References 29 publications

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“…Therefore, we can set weight values for different emphasis requirements, and the physical layout process also verifies the feasibility of the proposed methodology. In order to further verify the effectiveness of the design method applied to the physical layout (IP modules that have been taped) [28][29][30], we conducted an experimental comparison with a commercial EDA tool flow, where the commercial EDA tool flow is a fully automatic clock tree synthesis method. Based on the proposed clock mesh design method, we optimized the experimental results through a fine-tuning hierarchical clock network.…”

Section: Resultsmentioning

confidence: 99%

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

Li,

Feng,

Shen

et al. 2023

Preprint

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In light of advancing technology, the conventional clock network architecture has become inadequate for addressing the intricacies inherent in modern System-on-Chip (SoC) designs. While clock mesh topology offers resilience against On-Chip Variation (OCV) fluctuations, it still necessitates manual intervention. Therefore, substantial scope exists for methodological enhancements and the refinement of rapid analytical techniques. This paper introduces a novel clock mesh synthesis approach, underpinned by dynamic programming algorithms, that guarantees latency constraints. Our experimental findings demonstrate that our algorithm achieves an additional 26.6% reduction in power consumption compared to the baseline methodology. Furthermore, it substantially reduces runtime by an average of 78.0% when contrasted with traditional simulation methods. These results highlight the potential of our methodology for enhancing the efficiency and power management of clock mesh.

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Section: Resultsmentioning

confidence: 99%

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

Li,

Feng,

Shen

et al. 2023

Preprint

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“…In recent years, the rapid growth of emerging applications, including the Internet of Things, intelligent computing, and medical electronics, has driven increased market demand for application-specific integrated circuits (ASICs) [1][2][3]. Field Programmable Gate Arrays (FPGAs), known for their reconfigurable nature, offer flexible configuration and cost-effective engineering experimentation.…”

Section: Introductionmentioning

confidence: 99%

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Liu,

Wang,

2023

Electronics

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Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

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Progress in a novel architecture for high performance processing

Cited by 2 publications

References 29 publications

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

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