Progressive-Scan Rate Up-Conversion of 24/30 Hz Source Materials for HDTV

Bugwadia,; Petajan,; Puri,

doi:10.1109/icce.1996.517203

Cited by 8 publications

(7 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…FRUC can be done by interpolating a new frame between every two consecutive original frames like in 25 Hz to 50 Hz conversion, and it can be done by interpolating three new frames between every two consecutive original frames like in 25 Hz to 100 Hz conversion. In the case of 24 Hz to 60 Hz conversion, 3:2 pull-down technique is used [1]. FRUC for 1:4 conversion ratio is illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion

Ozcan

Cakir

Çetin

et al. 2011

2011 14th Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

Overlapped BlockMotion Compensation (OBMC) technique is used to avoid blocking artifacts occurring because of block based processing in video enhancement and compression applications. In this paper, we propose Weighted Coefficient OBMC (WC-OBMC) algorithm and an efficient hardware architecture for its implementation. WC-OBMC produces high quality results with low computational complexity for frame rate up conversion of High Definition (HD) video. The proposed hardware implementation of WC-OBMC algorithm consumes 20% of the slices in a Xilinx XC6SLX9-2 FPGA. It can work at 65 MHz in the same FPGA, and it is capable of processing 31 1280x720 HD frames per second.

show abstract

Section: Introductionmentioning

confidence: 99%

An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion

Ozcan

Cakir

Çetin

et al. 2011

2011 14th Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

show abstract

“…FRC can be done by interpolating a new frame between every two consecutive original frames like in 25 Hz to 50 Hz conversion, and it can be done by interpolating three new frames between every two consecutive original frames like in 25 Hz to 100 Hz conversion. In the case of 24 Hz to 60 Hz conversion 3:2 pull-down technique is used [1]. FRC for 1:4 conversion ratio is illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video

Tasdizen

Hamzaoğlu

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

View full text Add to dashboard Cite

Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. The proposed hardware architecture is implemented in VHDL and mapped to a low cost Xilinx XC3SD1800A-4 FPGA device. The implementation results show that the proposed hardware can run at 101 MHz on this FPGA and consumes 32 BRAMs and 15384 slices.

show abstract

“…In recent years a number of frame interpolation algorithms have been developed [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]. Most of them concentrate on high-frame-rate video as shown in Table 1 [1,2,3,4,5,6,7,8,9,10,11,12,13] and part of [16].…”

Section: Introductionmentioning

confidence: 99%

“…Most of them concentrate on high-frame-rate video as shown in Table 1 [1,2,3,4,5,6,7,8,9,10,11,12,13] and part of [16]. In such cases, motion estimation can be achieved by simple block-matching technique.…”

Section: Introductionmentioning

confidence: 99%

“…In the algorithms presented in this paper, the transmitted motion vectors are not used because for frame interpolation, true motion vector is needed for every pixel [17]. The transmitted motion vectors are not the true motion vectors and they are also produced for every (16 × Frame interpolation algorithms Frame-rate conversion (fps) [1] 50 to 75 [2,3] 24/30 to 60 [4,5] 10 to 30 [6,7,8,9] 15 to 30 [10] 10 to 30 and 15 to 30 [11,12] 50 to 100 [13] 12.5 to 25 [14] 7.5 to 30 [15] 3.75 to 15 [16] 10 to 30, 6 to 30, 12.5 to 50, and 8.3 to 50…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multiresolution Motion Estimation for Low-Rate Video Frame Interpolation

Karim

Bister

Siddiqi

2004

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

Interpolation of video frames with the purpose of increasing the frame rate requires the estimation of motion in the image so as to interpolate pixels along the path of the objects. In this paper, the specific challenges of low-rate video frame interpolation are illustrated by choosing one well-performing algorithm for high-frame-rate interpolation (Castango 1996) and applying it to low frame rates. The degradation of performance is illustrated by comparing the original algorithm, the algorithm adapted to low frame rate, and simple averaging. To overcome the particular challenges of low-frame-rate interpolation, two algorithms based on multiresolution motion estimation are developed and compared on objective and subjective basis and shown to provide an elegant solution to the specific challenges of low-frame-rate video interpolation.

show abstract

Progressive-Scan Rate Up-Conversion of 24/30 Hz Source Materials for HDTV

Cited by 8 publications

References 6 publications

An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion

An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion

A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video

Multiresolution Motion Estimation for Low-Rate Video Frame Interpolation

Contact Info

Product

Resources

About