Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

Abstract

In this paper we propose a novel projection-based algorithm to estimate the full-chip leakage power with consideration of both inter-die and intra-die process variations. Unlike many traditional approaches that rely on log-Normal approximations, the proposed algorithm applies a novel projection method to extract a low-rank quadratic model of the logarithm of the full-chip leakage current and, therefore, is not limited to log-Normal distributions. By exploring the underlying sparse structure of the problem, an efficient algorithm is developed to extract the non-log-Normal leakage distribution with linear computational complexity in circuit size. In addition, an incremental analysis algorithm is proposed to quickly update the leakage distribution after changes to a circuit are made. Our numerical examples in a commercial 90nm CMOS process demonstrate that the proposed algorithm provides 4x error reduction compared with the previously proposed log-Normal approximations, while achieving orders of magnitude more efficiency than a Monte Carlo analysis with 10 4 samples. Categories and Subject Descriptors INTRODUCTIONAs IC technologies move to nanoscale feature sizes, leakage power becomes increasingly large and significantly impacts the total chip power consumption. The predicted leakage power is expected to reach 50% of the total chip power within the next few technology generations [1]. Therefore, accurately modeling and analyzing leakage power has been identified as one of the top priorities for today's IC design problems.The most important leakage components in nanoscale CMOS technologies include sub-threshold leakage and gate tunneling leakage [2]. The sub-threshold leakage models the weak inversion conduction when gate voltage is below the threshold voltage. At the same time, the reduction of gate oxide thickness facilitates tunneling of electrons through gate oxide, creating the gate leakage. Both of these leakage components are significant for sub100nm technologies and must be considered for leakage analysis.Unlike many other performances (e.g., delay), leakage power varies substantially due to process variations, which increases the difficulty of leakage estimation. As demonstrated in [3], leakage variations can reach 20x, while delays only vary about 30%. It has also been observed that leakage power is sensitive to both interdie and intra-die variations. Intra-die variations model the individual, but spatially correlated, local variations within the same die. These intra-die variations must be modeled by many additional random variables, thereby significantly increasing the problem size of leakage analysis. For example, the total number of random variables can reach 10 3~1 0 6 to model the full-chip variations for a practical industry design.Many works have been developed to capture the leakage variations [4]- [10]. Most of these approaches approximate the leakage variation as a log-Normal distribution. For that purpose, a first-order (i.e., linear) Taylor expansion is used to approximate the logari...

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“…However, most of them (e.g., [7,5,[10][11][12][13]) either did not consider non-Gaussian parameter distributions, or did not include junction tunneling leakage that cannot be omitted for sub-65 nm CMOS technology. Recent work [14] took the above two issues into consideration.…”