Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Abstract

Ferroelectric materials are promising resources for boosting the performance of line or vertical tunneling-field transistors (VTFETs) by diminishing the voltage requirements. Here, we propose a promising VTFET design which has the benefits of HZO thin films having 50% of Zr composition on Hafnium oxide as Hf 0.5 Zr 0.5 O 2 . The significance of negative capacitance (NC) from Hf 0.5 Zr 0.5 O 2 on to VTFET is explored with the physical factors of the electric field and band-to-band tunneling. In addition, the significant factor of the internal-voltage due to NC is modeled using the metal-ferroelectric-insulator approach. The device on-and off-state currents are optimized with the key factor of vertical tunneling called overlapped source and drain regions for NCVTFET. Using an enhanced vertical tunneling area, hetero-structure (Si/SiGe), and ferroelectric options provides two-time improvement in I on by utilizing the ferroelectric rather than the nominal (without ferroelectric). The device also delivers 40-145 GHz of frequency with low orders (<1.0 fF) of gate-capacitance. The device provides ten-time improvement in I on and two-order reduction in energyefficiency compared to the explored ferroelectric structure.

Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

“…It is to be understood that hysteresis-free operation can be achieved on several factors, such as by reducing the t fe and maintaining |C fe |C g (addressed in later sections). It is found that the t fe 5 nm is delivered with low hysteresis [43][44][45][46], the same can be perceived through our simulations as stated in figure 4(a) [22]. For controlled I off , the P r and E c are adjusted to 10 μC cm −2 and 1 MVcm −1 (as stated before).…”

“…Figure1. Simulations are endorsed with the measurement data for a ferroelectric TFET structure[7,22].…”

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

“…Here, Q on and Q off represent the on-and off-charges of p-and n-CTFETs during on-and off-cycles. The factor of [32], ferroelectric utilization [28], low band bag semiconductors, and so on. As a future scope of CFET/CTFET, it is interesting to note the parasitic effect and their tradeoffs are challenging task in addition to FP H reduction (earlier stated).…”

Design and exploration of vertically stacked complementary tunneling field-effect transistors

“…As a prior demonstration, CFET technology utilization for TFETs is restricted to conventional or point-tunneling rather advanced-tunneling approaches i. [28][29][30][31] In conclusion, the proposal for the design and exploration of CTFETs utilizing CFET technology for emerging technology nodes has been successfully delivered. The physical analyses and DC characteristic behavior have been discussed while highlighting the ability of CTFET under strict process conditions.…”