Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition

Love, Eric; Jin, Yier; Makris, Yiorgos

doi:10.1109/tifs.2011.2160627

Cited by 146 publications

(61 citation statements)

References 19 publications

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“…Eric et al [9] showed that by assigning 3PIP vendor, the task of constructing compliance proofs for their hardware IP, consumers (SoC integrator) can make sure that the HW they purchase operates within the parameters they have chosen as provable security properties. This is basically an agreement between a SoC integrator and a 3PIP vendor on a pre-defined set of properties which can be verified by SoC integrator.…”

Section: Background and Related Workmentioning

confidence: 99%

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

Veeranna

Schafer

2017

J Hardw Syst Secur

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This work introduces a runtime system level method to detect hardware Trojan in third party behavioral intellectual properties (3PBIPs). Most of the HW Trojan detection techniques either rely on golden Trojanfree (trusted) models, which are compared to the suspected model, or source IPs with the same functionality from different vendors. In the case of BIPs, this is extremely hard, as it is a market still in its infancy. Moreover, it is very difficult to find HW Trojan at the system level as the trigger condition might be visible only when the system is fully functional. Thus, this work proposes the inclusion of a small HW Trojan detection circuit called trust filters to detect HW Trojan at runtime. With the help of cycle-accurate simulation model, it is possible to fine tune these filters so that the overall system has no performance degradation. This can be achieved by exploiting the slack time between the time that a slave returns the data to the master and the time that the master sends new data to the slave. The advantages of using C-based design are multi-fold: (i) It allows the generation of fast cycle-accurate models to measure the exact slack of each BIP mapped as a loosely coupled Hardware Accelerator (HWAcc) slave and (ii) its ability to build the complete SoC using synthesizable Application Programming Interfaces (APIs) and hence allowing the fine tuning of these trust filters. Experimental results show that our proposed architecture is very efficient leading to no performance penalties in many cases and has very small area overhead.Keywords High-level synthesis · Hardware trojan · Behavioral MPSoC · Third party behavioral IP (3PBIP)

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Section: Background and Related Workmentioning

confidence: 99%

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

Veeranna

Schafer

2017

J Hardw Syst Secur

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“…The recent efforts around the Proof Carrying Hardware (PCH) [18,19,8], inspired by the research about Proof Carrying Code (PCC), is promising. The main idea behind PCH is to derive a model from a hardware device implementation written in a Hardware Description Language (HDL).…”

Section: Related Workmentioning

confidence: 99%

“…Therefore, the equivalence between the model and the implementation has to be established. In this perspective, the Proof Carrying Hardware framework [7,18,19,8] is particulary interesting and we intend to investigate in this direction.…”

Section: Related Workmentioning

confidence: 99%

SpecCert: Specifying and Verifying Hardware-Based Security Enforcement

Letan

Chifflier

Hiet

et al. 2016

FM 2016: Formal Methods

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Abstract. Over time, hardware designs have constantly grown in complexity and modern platforms involve multiple interconnected hardware components. During the last decade, several vulnerability disclosures have proven that trust in hardware can be misplaced. In this article, we give a formal definition of Hardware-based Security Enforcement (HSE) mechanisms, a class of security enforcement mechanisms such that a software component relies on the underlying hardware platform to enforce a security policy. We then model a subset of a x86-based hardware platform specifications and we prove the soundness of a realistic HSE mechanism within this model using Coq, a proof assistant system.

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“…Yet these techniques are not quite effective for trojans in 3PIPs since there is no golden (trojan-free) model for the designer to refer to. Neither are techniques used to detect design bugs, such as RTL verification, effective for detecting trojans in 3PIPs [12], since they are very time consuming and do not scale for complex MPSoCs.…”

Section: A Security Challenges In Mpsoc Designmentioning

confidence: 99%

“…As these techniques require detailed RTL information, their application to third-party IP cores is limited. Another related work [12] requires the check of a 3PIP against pre-defined agreements on security related properties provided by the vendor. Yet developing security related properties for a 3PIP is still in its infancy.…”

Section: Related Workmentioning

confidence: 99%

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling

Liu

Rajendran

Yang

et al. 2013

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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Outsourcing of the various aspects of IC design and fabri cation flow strongl y questions the classic assumption that "hardware is trustworth y ". Multiprocessor S y stem-on-Chip (MPSoC) platforms face some of the most demanding securit y concerns, as they process, store, and communicate sensitive information using third-part y intellectual property (3PIP) cores that ma y be untrustworth y . The complexit y of an MPSoC makes it expensive and time consuming to full y anal y ze and test it during the design stage. Consequently, the trustworthiness of the 3PIP components cannot be ensured. To protect MPSoCs against malicious modifications, we propose to incorporate trojan toleration into MPSoC platforms b y revising the task scheduling step of the MPSoC design process. We impose a set of securit y -driven diversit y constraints into the scheduling process, enabling the s y stem to detect the presence of malicious modifications or to mute their effects during application execution. Furthermore, we pose the securit y -constrained MPSoC task scheduling as a multi-dimensional optimization problem, and propose a set of heuristics to ensure that the introduced securit y constraints can be fulfilled with minimum performance and hardware overhead.

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Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition

Cited by 146 publications

References 19 publications

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

SpecCert: Specifying and Verifying Hardware-Based Security Enforcement

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling

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