“…For the clock jitter and skew, the data transmitted between SDI and FPGA equipment would become redundancy or discontinuity. At present,experts have put much effort in resolving clock synchronization by PLL(Phase Lock loop, a phase-locked loop clock synchronization method [1][2] ).It's said that PLL is one of the most effective methods to track phase and frequency.But it could not acquird the requirements of clock synchronization for uncompressed burst data quickly.Furthermore, traditional synchronization technology ,such as GPS,SDH/PHD,all required expensive and high precision crystal oscillator [3] .Recently, most of researches interest in the complicated algorithm,such as RBS [4] , DMTS [5] , FTSP [6] , AD [7] , TPSN [8] , TS/MS [9] etc.Most of them put much effort on how to compensate the clock offset,but not interest in the resolving the drift.To resolve it ,a "reservoir"method is proposed.But it need a buffer memory deep enough.As the OFDM_MIMO system is considered,this buffer memory would waste much resource.So the target of our study is to find a resolution to eliminate the clock jitter and skew without additional hard ware and with fewer resource.…”