Property specific information flow analysis for hardware security verification

Hu, Wei; Ardeshiricham, Armaiti; Gobulukoglu, Mustafa; Wang, Xinmu; Kastner, Ryan

doi:10.1145/3240765.3240839

Cited by 30 publications

(16 citation statements)

References 21 publications

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“…The RTLIFT logic can be analyzed by the available EDA tools, eliminating the need for designing a new type system. A property specific approach for information flow security was proposed to accelerate security verification and restrict potential security violations to quickly pinpoint hardware security vulnerabilities [22] .…”

Section: Related Workmentioning

confidence: 99%

A multi-flow information flow tracking approach for proving quantitative hardware security properties

Tai

Zhang

et al. 2021

Tinshhua Sci. Technol.

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Information Flow Tracking (IFT) is an established formal method for proving security properties related to confidentiality, integrity, and isolation. It has seen promise in identifying security vulnerabilities resulting from design flaws, timing channels, and hardware Trojans for secure hardware design. However, existing IFT methods tend to take a qualitative approach and only enforce binary security properties, requiring strict non-interference for the properties to hold while real systems usually allow a small amount of information flows to enable desirable interactions. Consequently, existing methods are inadequate for reasoning about quantitative security properties or measuring the security of a design in order to assess the severity of a security vulnerability. In this work, we propose two multi-flow solutions -multiple verifications for replicating existing IFT model and multi-flow IFT method. The proposed multi-flow IFT method provides more insight into simultaneous information flow behaviors and allows for proof of quantitative information flow security properties, such as diffusion, randomization, and boundaries on the amount of simultaneous information flows. Experimental results show that our method can be used to prove a new type of information flow security property with verification performance benefits.

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Section: Related Workmentioning

confidence: 99%

A multi-flow information flow tracking approach for proving quantitative hardware security properties

Tai

Zhang

et al. 2021

Tinshhua Sci. Technol.

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“…Table IV shows information flow properties for AES and RSA implementations. These properties are collected from work on gate level information flow tracking [20] and were, to the best of our knowledge, developed manually.…”

Section: Hardware Security Propertiesmentioning

confidence: 99%

“…To evaluate Transys on the AES and RSA designs, we draft 17 assertions for 3 designs to feed as input to Transys (see Table VII). We also collect 14 information-flow security assertions for AES and RSA cores from the IFT Model project [20] (see Table IX). These assertions are drafted for 3 AES and 3 RSA implementations, and cover properties about confidentiality, integrity, isolation and timing channels.…”

Section: A Experiments Setup and Datasetmentioning

confidence: 99%

Transys: Leveraging Common Security Properties Across Hardware Designs

Zhang

Sturton

2020

2020 IEEE Symposium on Security and Privacy (SP)

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This paper presents Transys, a tool for translating security critical properties written for one hardware design to analogous properties suitable for a second design. Transys works in three passes adjusting the variable names, arithmetic expressions, logical preconditions, and timing constraints of the original property to retain the intended semantics of the property while making it valid for the second design. We evaluate Transys by translating 27 assertions written in a temporal logic and 9 properties written for use with gate level information flow tracking across 38 AES designs, 3 RSA designs, and 5 RISC processor designs. Transys successfully translates 96% of the properties. Among these, the translation of 23 (64%) of the properties achieved a semantic equivalence rate of above 60%. The average translation time per property is about 70 seconds.

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“…The information flow analysis could not cover all information flows as the design scale increasing. Hu et al (2018) employ specified security properties written by the security expertise to relieve the information flow redundancy. While, it also needs a large amount of verification resource to get a good Trojan coverage, including both verification time, design area overhead and security expertise.…”

Section: Hardware Trojans Detectionmentioning

confidence: 99%

“…Many HTs detection technologies (e.g. information flow analysis (Hu et al 2018), logic testing (Dupuis et al 2018) and formal methods) are too time-consuming to cover the entire state space in complex designs. Security verification resources, are the factor related to the security coverage of verification result, like the verification time, the sophistication of the methods, or the dedicated verification engineers available.…”

Section: Introductionmentioning

confidence: 99%