Proposal for Surface Tunnel Transistors

Abstract

A new three-terminal tunnel device, the surface tunnel transistor (STT), is proposed and its operation is demonstrated using GaAs/AlGaAs. STT consists of n+/i/p+ diode structure with an insulated gate in the i-region, which is similar to a MOSFET. However, the source and drain are oppositely doped. The most important feature of this device is that the drain must be so highly degenerated that a tunnel junction is formed with a two-dimensional (2D) electron channel under the gate. The tunneling current from source to drain is controlled by the gate bias through the concentration of accumulated 2D electrons under the gate. GaAs STTs with i-Al0.6Ga0.4As as a gate insulator are fabricated using MBE regrowth techniques on a mesa structure. This device exhibits transistor characteristics at 77 K and at room temperature, which confirms the new operation principle of STTs.

Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic

“…These include the capacitance associated with the actuation air gap, ε o A/(g − g d ), and the fixed parasitic capacitance C. In addition, there will be an actuation-area-dependent extrinsic capacitance (e.g., due to wire routing). Assuming an area proportionality factor r and an average relay activity factor a, the switching energy of a relay can be modeled by the following equation 2 :…”

“…Therefore, alternative transistor designs that can achieve steeper switching behavior than a MOSFET have been proposed to alleviate this issue [2]- [5]. However, any CMOS or CMOSlike technology will have a lower limit in energy per operation due to I OFF [6].…”

Introduction

“…The tunnel FET (also referred to as TFET) is based on electron tunneling through a barrier and is a promising solution for low-voltage and low-power applications. In particular, the TFET is aimed at supply voltages below 0.5 V. Early proposals of the TFET concept include [6,7]. TFETs have been investigated with different materials for the channel, namely carbon nanotubes, silicon and germanium.…”

Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

“…1. Several groups are working on the optimization of different device architectures [3][4][5][6][7][8][9][10]. In the offstate the TFET works as a reverse biased junction diode comprising a smaller static leakage current compared to the standard MOSFET.…”