Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Abstract

A new 800 V-class lateral high-voltage n-channel MOS (HVNMOS) structure with a markedly reduced parasitic capacitance (C oss ) has been developed for integration in a high-voltage gate driver IC. In our new HVNMOS, a 40% C oss reduction from that of a conventional HVNMOS can be achieved by using two n-type drift regions divided by a p-type diffusion layer. We have confirmed that a 12% shorter I/O propagation delay time can be achieved by using the new HVNMOS of the high-voltage IC (HVIC) test chip. In this paper, the design concept of the developed HVNMOS is presented with the simulation and experimental results.