Proposed triple hill cipher algorithm for increasing the security level of encrypted binary data and its implementation using FPGA

Khalaf, Ashraf A. M.; El-karim, Mona S. Abd; Hamed, Hesham F. A.

doi:10.1109/icact.2015.7224836

Cited by 5 publications

(1 citation statement)

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“…FPGA implementation of Xilinx Synthesis Tool on Vertex II pro kit Show synthesis results, also it provides computation time for generating the cipher text by AES with 4 S-box and 2 dual ports RAM is 6.922 ns. A triple hill cipher algorithm was introduced and implemented by FPGA [11]. The main goal of this research was to make the algorithm more robust by using three stages of a modified hill cipher; every stage is considered a block cipher with a block length of 128 bits and key length of 256 bits, the plain text to be encrypted is processed by this block cipher in three stages to increase the security.…”

Section: Background and Previous Research 21 Related Workmentioning

confidence: 99%

Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA

Sarhan¹,

Fayez²,

Hussen³

2017

IJCA

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Due to the rapid use of Internet technology, a need for security mechanisms has appeared to protect the information. Cryptography is one of the most effective techniques used to protect and secure information. Triple Data encryption standard is a cryptography system that provides security in the commercial enterprise. A lot of research has been made over DES and Triple DES algorithms to enhance their performance. In this paper, an Enhanced Triple-DES Algorithm based on Cluster LUT (Look Up Table) and Pipelining (ETDCP) is proposed, as a modification of the Triple DES. ETDCP algorithm uses Cluster LUT in hardware implementation and uses the large embedded memories available in the SPARTAN-E FPGA as hardware designed to obtain the minimum utilized resource. Using cluster LUT diminishes the consumption power by reducing the number of registers and slice/area, which decreases the number of logic utilizations used for Spartan Xilinx FPGA. In addition, ETDCP uses pipelining techniques which will increase the processing rate. The experimental results are based on simulated and synthesized (Xilinx Spartan-E) using ModelSim 6.5 and VHDL code. The results show high throughput/area FPGA implementation. The simulation result also proves that the proposed FPGA implementation of ETDCP algorithm has better speed performance compared to previous implementations of cryptographic algorithms.

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Section: Background and Previous Research 21 Related Workmentioning

confidence: 99%