Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects

Thacker, Hiren; Meindl, J.D.

doi:10.1109/test.2006.297668

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Mesh Pinch-off Results1

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2010

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“…Figure 9 shows the pinch-off results of varying mesh sizes. Pulse chronopotentiometry provides a better concentration gradient of cupric ions in the via as compared to conventional chronopotentiometry [3,11]. Plating was conducted at a beaker scale in the lab, and additional agitation was provided by electrode rotation using a magnetic stirring bar.…”

Section: Mesh Pinch-off Resultsmentioning

confidence: 99%

A ‘mesh’ seed layer for improved through-silicon-via fabrication

Lai¹,

Yang²,

Chen³

et al. 2010

J. Micromech. Microeng.

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This paper describes an improved method of forming and removing seed layers for through-silicon-vias (TSVs) in applications such as MEMS, sensors and packaging (silicon carrier, for example). A 'mesh seed layer' is proposed to reduce the pinch-off time and facilitate simpler and mechanical-free removal, the latter being possibly important when sensitive MEMS/sensor devices are pre-fabricated on the wafer. As a result, the proposed process may serve as a post-MEMS/sensor method of forming TSVs.

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Section: Mesh Pinch-off Resultsmentioning

confidence: 99%