Protected IP-core test generation

Abstract

Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. IPs are usually provided with their own test patterns that can be used only by applying design for testability techniques onto the chip. Whenever physical faults must be detected, this approach is reasonable, even if it implies circuit performance degradation. However, it is completely useless at the design level, when the correct integration of the IPs into the global design must be investigated. At this level, proprietary test sequences must be generated in relation to the actual use of the IPs into the design. In this paper, the SystemC language is exploited to define a design verification framework for integration test of IP-cores. Intellectual properties of cores are guaranteed by adopting a client/server simulation architecture and by allowing functional test generation on faulty IP-core models without disclosing their internal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC. Finally, remote simulation can be also performed locally to avoid bandwidth bottleneck and the test generation process can be indifferently applied at lower abstraction levels such as RT and gate.