Protecting against emerging vmin failures in advanced technology nodes

Abstract

As technology and voltage scale, both intrinsic and extrinsic Vmin failures can occur at a significant rate. These failures can impact yield and reliability. We propose a novel guardband and advanced outlier limits (AOL) methodology to protect against intrinsic and extrinsic Vmin failures. This paper will demonstrate the impact of aging, RTN and HKMG process variation on Vmin. The data will be used to establish guardbands and AOL to minimize failures during testing and in the field. IntroductionTechnology advancements in Big Data and the data center are putting pressure on memory suppliers to deliver much more memory in smaller packages with lower power and higher reliability. In order to meet these requirements, memory suppliers are pushing the operating voltages closer and closer to Vmin (the minimum voltage level at which a part will reliably operate). The operating margins with respect to Vmin are therefore becoming tighter, and increasing the likelihood of failures. This increase in failure rate is in addition to the failures that naturally occur based on the sheer amount of memory in the data center.As a consequence of technology scaling, process variations, aging, RTN (Random Telegraph Noise), which increases device V t, has become a dominant mechanism degrading device maximum operating frequency (F max ) and minimum operating voltage (V min ). For a device with overdrive (V dd -V t ), an increase in V t requires an increase in minimum V dd to maintain same overdrive, hence V min shift is proportional to V t shift [1]. Vmin is a risk indicator that is based on potential conditions described above.Furthermore to enable higher performance at lower voltage and lower leakage levels, the transistor gate oxide has moved from silicon oxynitride / poly gate (SiON/Poly) to high-k / metal gate (HKMG) which further has reduced intrinsic reliability margin [2]; requiring more novel guard banding and screening techniques for reliability.Complicating matters even further, memory content has doubled for each technology generation which compounds the challenges faced by shrinking memory cells. In deeply scaled technologies, local Vt fluctuations, BTI and RTN are the three biggest issues [3] impacting the margin between the operating supply voltage (Vdd) and the minimum supply voltage below which an SRAM cell cannot be operated (Vmin). Scaling to 0.5X SRAM cell size constant Vmin becomes difficult. Since Vt cannot be scaled down aggressively, due to short channel effect, power-supply voltage (Vdd) has not been scaled down in proportion to the MOSFET channel length. This is especially true for SRAM due to shrinking headroom and rising Vmin. The impact of memory bit cell density and its Vmin trade-off is significant and the risk needs to be mitigated.There is plenty of published work which discusses the BTI impact on parametric or Vmin drift, including [4,5]. However, details regarding comprehensive protection against Vmin failures are very limited. In this paper, we present a methodology to analyze the various contributions...

Component and system effective lifetime & FIT model in advanced technology

“…As shown in slope m~0.15-0.2 was found for ex failures (memory + non-memory) b unscreened for outliers [9] so that failures. For extrinsic late life failure a Weibull slope m~2-2.5 due to HK expected and validated by stressing and counting failing bits at the know (~0.75V) [10]. …”