Protecting analog circuits with parameter biasing obfuscation

Rao, Vaibhav Venugopal; Savidis, Ioannis

doi:10.1109/latw.2017.7906739

Cited by 31 publications

(27 citation statements)

References 8 publications

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“…In [16], it is proposed to lock the body-biasing of a matched transistor pair with a lock mechanism that is based on a memristor crossbar, where the key-bits control the programming of the memristors. In [17], it is proposed to replace the transistors used to set the biasing with parallel-connected transistors. The key-bits control which of these transistors are "on", where the aggregate width of the "on" transistors equals the width of the original obfuscated transistor.…”

Section: Prior Art In Analog Ic Locking and Obfuscationmentioning

confidence: 99%

Analog and Mixed-Signal IC Security via Sizing Camouflaging

Leonhard

Sayed

Louërat

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We treat the problem of analog Integrated Circuit (IC) obfuscation towards Intellectual Property (IP) protection against reverse engineering. Obfuscation is achieved by camouflaging the effective geometry of layout components via the use of fake contacts, which originally were proposed for gate camouflaging in digital ICs. We present a library of obfuscated layout components, we give recommendations for effective camouflaging, we discuss foreseen attacks and the achieved resiliency, and we propose security metrics for assessing the hardness of reverse engineering. The proposed methodology is demonstrated on an operational amplifier and an RF Σ∆ Analog-to-Digital Converter (ADC).

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Section: Prior Art In Analog Ic Locking and Obfuscationmentioning

confidence: 99%

Analog and Mixed-Signal IC Security via Sizing Camouflaging

Leonhard

Sayed

Louërat

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In [11], it is proposed to replace transistors within the biasing circuit with parallel-connected transistors whose gates are controlled by key bits. The key bits enable transistors whose aggregate width equals that of the original transistor.…”

Section: Previous Work On Analog Ic Lockingmentioning

confidence: 99%

MixLock: Securing Mixed-Signal Circuits via Logic Locking

Leonhard

Yasin

Turk

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In this paper, we propose a hardware security methodology for mixed-signal Integrated Circuits (ICs). The proposed methodology can be used as a countermeasure for IC piracy, including counterfeiting and reverse engineering. It relies on logic locking of the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. We employ a state-of-the-art logic locking technique, called Stripped Functionality Logic Locking (SFLL). We show that strong security levels are achieved in both mixed-signal and digital domains. In addition, the proposed methodology presents several appealing properties. It is non-intrusive for the analog section, it incurs reasonable area and power overhead, it can be fully automated, and it is virtually applicable to a wide range of mixed-signal ICs. We demonstrate it on a Σ∆ Analog-to-Digital Converter (ADC).

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“…3. More specifically, in [11], it is proposed to replace biasing transistors with parallel-connected transistors whose gates are controlled by key bits. The key bits enable transistors whose aggregate width equals that of the original biasing transistor.…”

Section: Introductionmentioning

confidence: 99%

“…Perhaps [13] provides the highest resilience against removal attacks since the design of the digital section is intertwined with the design of the analog section, thus replacement by redesign is not straightforward. In addition, the locking approaches in [11], [12] act on the biasing of the circuit and, thereby, the attacker does not have to recover the key; it suffices to recover the biases, which are typically small in number.…”

Section: Introductionmentioning

confidence: 99%

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Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application

Leonhard¹,

Louërat²,

Aboushady³

et al. 2019

2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (

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In this paper, we demonstrate a recently proposed security technique for mixed-signal circuits in the context of a real application. The security technique, called MixLock, is based on logic locking of the digital section of the mixed-signal circuit and can be used as a countermeasure for reverse engineering and counterfeiting. We demonstrate MixLock in an audio application, where the underlying Σ∆ ADC that digitizes the audio input is locked. We show the effect that locking has on the recorded audio quality based on a metric that counts the resultant glitches per second and by also providing a link where the interested reader can download and listen to output audio samples for locked and unlocked versions of the Σ∆ ADC.

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Protecting analog circuits with parameter biasing obfuscation

Cited by 31 publications

References 8 publications

Analog and Mixed-Signal IC Security via Sizing Camouflaging

Analog and Mixed-Signal IC Security via Sizing Camouflaging

MixLock: Securing Mixed-Signal Circuits via Logic Locking

Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application

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