Protection Circuit against Differential Power Analysis Attacks for Smart Cards

Mureşan, Radu; Gregori, Stefano

doi:10.1109/tc.2008.107

Cited by 41 publications

(23 citation statements)

References 11 publications

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“…The main difference is that our application requires a current waveform between clock periods as identical as possible, while imperfections in cryptographic hardware can be compensated with other techniques such as random masking [41] and current flattening [42]. The proposed approach does also differ from the methods discussed in the previous section, which focus on reducing SSN in the time domain, while this work focuses on reducing SSN in the frequency domain.…”

Section: Noise Reduction Methodsmentioning

confidence: 99%

Reduction of Substrate Noise in Sub Clock Frequency Range

Sherazi

Asif

Backenius³

et al. 2010

IEEE Trans. Circuits Syst. I

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Abstract-We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.Index Terms-Flip-flops, integrated circuit noise, mixed analogdigital integrated circuits, simultaneous switching noise, substrate noise.

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Section: Noise Reduction Methodsmentioning

confidence: 99%

Reduction of Substrate Noise in Sub Clock Frequency Range

Sherazi

Asif

Backenius³

et al. 2010

IEEE Trans. Circuits Syst. I

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“…The DPA attack is used to reduce the noise performance [10], but it is important to investigate other strategies leading to further reduction in the amount of noise. Noise can be classified as External, Internal, and Quantization.…”

Section: Noise Analysis Attackmentioning

confidence: 99%

A Novel and Efficient countermeasure against Power Analysis Attacks using Elliptic Curve Cryptography

Prabu¹,

Shanmugalakshmi²

2010

IJACSA

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Abstract-Recently, there is a leakage in the communication channel information by the cryptographic processors. It is the major chore to overcome the pouring out or spreading out of the secure data. In this paper, a new level of security analysis model is constructed in power analysis using Elliptic Curve Cryptography. And so many side channel attacks and their countermeasures are explained undeniably. An algorithm design based on power analysis is also described and it makes our countermeasure more secure against simple power analysis, differential power analysis and other attacks. The theoretical analysis based on these result has been shown and it represents how the algorithm design should fluctuate from the facade side channel attacks.

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“…In [13] the resistance of a current flattening circuit against DPA attack has been investigated. Thousands current traces were collected at the supply pin of a standard 8-bit microcontroller (ATmega 16L) executing DES encryption.…”

Section: Designmentioning

confidence: 99%

Improved current flattening circuit using current injection, voltage regulation, and frequency switching

Vahedi

Gregori

Mureşan

2008

2008 Canadian Conference on Electrical and Computer Engineering

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This paper presents a current-flattening circuit which combines current injection, voltage regulation, and frequency switching methods. The circuit can protect a cryptographic device, such as a smart card, against differential power analysis attack. The proposed circuit can be integrated with any type of cryptographic processor and does not need any interface with the processor. Simulation results show that the variations in the power supply current profile is attenuated by 92%, while the power consumption overhead is less than 12% of the original power consumption of the cryptographic processor.

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Protection Circuit against Differential Power Analysis Attacks for Smart Cards

Cited by 41 publications

References 11 publications

Reduction of Substrate Noise in Sub Clock Frequency Range

Reduction of Substrate Noise in Sub Clock Frequency Range

A Novel and Efficient countermeasure against Power Analysis Attacks using Elliptic Curve Cryptography

Improved current flattening circuit using current injection, voltage regulation, and frequency switching

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