Proteus

Shin, Seunghee; Tirukkovalluri, Satish Kumar; Tuck, James; Solihin, Yan

doi:10.1145/3123939.3124539

Cited by 85 publications

(7 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A second way to categorize these mechanisms is by the crash consistency technique adopted. The most common is by logging, which subdivides into redo-logging, 2,8,10,11,14,15,[20][21][22][23][24] undo-logging, 9,16,18,19,25 or a hybrid proposal of both. 26,27 Furthermore, other works have implemented shadow-paging, 1,28,29 logging-structured 30 and out-of-placing 3 techniques.…”

Section: Related Workmentioning

confidence: 99%

“…Hardware mechanisms mitigate software approaches' runtime overhead persisting data adding no instructions, thereby eliminating software persistence barriers. Exceptions to this hardware flush procedure are ATOM, 9 Proteus, 25 and SSP, 29 which persist via software flush using hardware to manage logs earlier in order to keep them outside the critical execution path. Hardware-based approaches use several persistence techniques, such as shadow-paging 1,29,41 and out-of-place updates proposed by HOOP, 3 but the most common is write-ahead logging (WaL), varying from undo-logging, 9,16,19,25 redo-logging, 2,10,14,15,[21][22][23] or a hybrid approach of undo + redo logging.…”

Section: Hardware-basedmentioning

confidence: 99%

“…Exceptions to this hardware flush procedure are ATOM, 9 Proteus, 25 and SSP, 29 which persist via software flush using hardware to manage logs earlier in order to keep them outside the critical execution path. Hardware-based approaches use several persistence techniques, such as shadow-paging 1,29,41 and out-of-place updates proposed by HOOP, 3 but the most common is write-ahead logging (WaL), varying from undo-logging, 9,16,19,25 redo-logging, 2,10,14,15,[21][22][23] or a hybrid approach of undo + redo logging. 26,27 These works use logging hardware to generate log entries and coordinate data write-backs in the background, overlapping persistence with execution.…”

Section: Hardware-basedmentioning

confidence: 99%

“…26,27 These works use logging hardware to generate log entries and coordinate data write-backs in the background, overlapping persistence with execution. These log procedures can be managed by the load/store unit, 25 the coherence controller, 42 the cache controller, 15,19,21,23,27,43 or the memory controller. 1,9,44 Despite being hardware, most of them 2,3,9,[14][15][16]21,23,[25][26][27]29 are non-software-transparent, depending on programming models PTM-based to indicate atomic transactions, being hardware restricted to handle logs and checkpoint metadata.…”

Section: Hardware-basedmentioning

confidence: 99%

See 3 more Smart Citations

DONUTS: An efficient method for checkpointing in non‐volatile memories

Kruger

Pannain

Azevedo

2023

Concurrency and Computation

View full text Add to dashboard Cite

Non-volatile memory (NVM) is an emerging technology being explored as an alternative to DRAM main memory in computing systems because of its persistence, higher storage density, lower energy consumption, and access latency close to DRAM. However, persistent memory systems must ensure data consistency on system failures, a property known as crash consistency. One of the main challenges in these systems is creating efficient checkpointing mechanisms in terms of performance and usability. Thus, it is necessary to remove persistence from the critical execution path and reduce the excessive number of writes to NVM caused by logging operations, resulting in increased memory bandwidth usage. Another limitation is that most proposed mechanisms restrict application source code to programming interfaces based on transactional models, typed as software-based approaches. These factors make it challenging to adopt NVM systems. This article presents a software-transparent mechanism based on dynamic epochs with logging operations via processing-in-memory and checkpoints integrated into the cache replacement policy. Compared to the previous best-performing system, our strategy reduces 50.6% of writes to NVM. Furthermore, it does not increase the average memory bandwidth usage, providing crash consistency with less than 2% runtime overhead.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Hardware-basedmentioning

confidence: 99%

Section: Hardware-basedmentioning

confidence: 99%

Section: Hardware-basedmentioning

confidence: 99%

See 2 more Smart Citations

DONUTS: An efficient method for checkpointing in non‐volatile memories

Kruger

Pannain

Azevedo

2023

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…The number of NVM writes is reduced by eliminating the unnecessary evictions from the counter cache, which waives significant performance overheads. Proteus [41] is a hardware logging technique that provides two new instructions to create a log entry and to store the entry data to NVM as well as hardware support for transactions' durability. While the log space is specified by the program, several log registers are added to the register file, and a log pending queue is used to keep log operations out of the way of regular write-backs.…”

Section: Related Workmentioning

confidence: 99%

Compiler-support for Critical Data Persistence in NVM

Elkhouly

Alshboul

Hayashi

et al. 2019

ACM Trans. Archit. Code Optim.

Self Cite

View full text Add to dashboard Cite

Non-volatile Main Memories (NVMs) offer a promising way to preserve data persistence and enable computation recovery in case of failure. While the use of NVMs can significantly reduce the overhead of failure recovery, which is the case with High-Performance Computing (HPC) kernels, rewriting existing programs or writing new applications for NVMs is non-trivial. In this article, we present a compiler-support that automatically inserts complex instructions into kernels to achieve NVM data-persistence based on a simple programmer directive. Unlike checkpointing techniques that store the whole system state, our technique only persists user-designated objects as well as some parameters required for safe recovery such as loop induction variables. Also, our technique can reduce the number of data transfer operations, because our compiler coalesces consecutive memory-persisting operations into a single memory transaction per cache line when possible. Our compiler-support is implemented in the LLVM tool-chain and introduces the necessary modifications to loop-intensive computational kernels (e.g., TMM, LU, Gauss, and FFT) to force data persistence. The experiments show that our proposed compiler-support outperforms the most recent checkpointing techniques while its performance overheads are insignificant. CCS Concepts: • Software and its engineering → Source code generation; Runtime environments; Main memory; • Hardware → Emerging languages and compilers;

show abstract

An Adaptive Logging Framework for Persistent Memories

Poudel

Sharma

2018

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Proteus

Cited by 85 publications

References 35 publications

DONUTS: An efficient method for checkpointing in non‐volatile memories

DONUTS: An efficient method for checkpointing in non‐volatile memories

Compiler-support for Critical Data Persistence in NVM

An Adaptive Logging Framework for Persistent Memories

Contact Info

Product

Resources

About