Prototype of a gigabit data transmitter in 65nm CMOS for DEPFET pixel detectors at Belle-II

Abstract

a b s t r a c tThis paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via $ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1s distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Belle II PXD Detector

“…It was tested up to a bandwidth of 1.6 Gbps. [6] An eye-diagram to check the link stability is shown in Figure 4. The opening of the eye determines the quality of the data transmission, in this case it is still sufficiently open to ensure a stable connection.…”

65 nm Technology for HEP: Status and Perspective

“…ATLAS, CMS and CLIC are not the only projects studying the feasibility of 65 nm technologies in HEP. Other noticeable examples include Belle-II, which uses a gigabit data transmitter which was developed using the same technology [8]. This chip features high speed links running at 1.6 Gbit/s, with a total bandwidth of up to 6.4 Gbit/s, used to read out DEPFET modules in the detectors.…”

Recent Status of Front-end Electronics for DEPFET pixel detectors for Belle-II

“…The basic idea of the pre-emphasis is boosting the high-frequency components and cancel with the low-pass characteristics of the transmission cable. More information about the actual implementation for the PLL and CML driver can be found in [6].…”