Proving Liveness by Backwards Reachability

Abdulla, Parosh Aziz; Jönsson, Bengt; Rezine, Ahmed; Saksena, Mayank

doi:10.1007/11817949_7

Cited by 10 publications

(16 citation statements)

References 37 publications

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“…In particular, we have shown how the logic can capture quite a strong model of parameterised systems, incorporating more complex aspects of asynchrony and communication, and is also able to verify more sophisticated liveness and fairness properties. Thus, in contrast to many other approaches [23,9,2], not only safety, but also liveness and fairness properties, can be verified through (complete) automatic deductive verification.…”

Section: Discussionmentioning

confidence: 99%

“…In assessing the reliability of these systems, formal verification is clearly desirable and so several approaches have been developed. Two of the most popular are model checking for parameterised and infinite state-systems [1,2] and constraint based verification using counting abstractions [8,9,13], but both suffer problems. Within the model checking approach, formulae are translated into a Büchi transducer.…”

Section: Introductionmentioning

confidence: 99%

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Practical First-Order Temporal Reasoning

Dixon

Fisher

Konev

et al. 2008

2008 15th International Symposium on Temporal Representation and Reasoning

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Practical First-Order Temporal Reasoning

Dixon

Fisher

Konev

et al. 2008

2008 15th International Symposium on Temporal Representation and Reasoning

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show abstract

“…False properties, for which a counterexample was found, are marked "(f)". In the table, we compare our times with the works [27,3,5], as they use similar techniques, and were in fact timed on the same system. We also present related work, in alphabetical order with respect to authors.…”

Section: Resultsmentioning

confidence: 99%

“…[5] These techniques compute states which are guaranteed to satisfy ψ(i) using backwards reachability, thus avoiding the repeated reachability problem. However, they are not able to produce counterexamples, and are sometimes slower (due to requiring many accelerations).…”

Section: Resultsmentioning

confidence: 99%

“…These approaches require that a system can be verified using assertions of a certain form. In our earlier work [5], we proved liveness properties by backwards reachability analysis from "terminated" configurations; this technique can be combined with other techniques for proving liveness, but can not be used to find counterexamples (bugs); our technique is based on state-space exploration, which is guaranteed to report counterexamples when they exist.…”

Section: Introductionmentioning

confidence: 99%

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Systematic Acceleration in Regular Model Checking

Jönsson

Saksena

Computer Aided Verification

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Abstract. Regular model checking is a form of symbolic model checking technique for systems whose states can be represented as finite words over a finite alphabet, where regular sets are used as symbolic representation. A major problem in symbolic model checking of parameterized and infinite-state systems is that fixpoint computations to generate the set of reachable states or the set of reachable loops do not terminate in general. Therefore, acceleration techniques have been developed, which calculate the effect of arbitrarily long sequences of transitions generated by some action. We present a systematic method for using acceleration in regular model checking, for the case where each transition changes at most one position in the word; this includes many parameterized algorithms and algorithms on data structures. The method extracts a maximal (in a certain sense) set of actions from a transition relation. These actions, and systematically obtained compositions of them, are accelerated to speed up a fixpoint computation. The extraction can be done on any representation of the transition relation, e.g., as a union of actions or as a single monolithic transducer. Using this approach, we are for the first time able to verify completely automatically both safety and absence of starvation properties for a collection of parameterized synchronization protocols from the literature; for some protocols, we obtain significant improvements in verification time. The results show that symbolic statespace exploration, without using abstractions, is a viable alternative for verification of parameterized systems with a linear topology.

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Liveness of Randomised Parameterised Systems under Arbitrary Schedulers

Lin

Rümmer

2016

Computer Aided Verification

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Abstract. We consider the problem of verifying liveness for systems with a finite, but unbounded, number of processes, commonly known as parameterised systems. Typical examples of such systems include distributed protocols (e.g. for the dining philosopher problem). Unlike the case of verifying safety, proving liveness is still considered extremely challenging, especially in the presence of randomness in the system. In this paper we consider liveness under arbitrary (including unfair) schedulers, which is often considered a desirable property in the literature of self-stabilising systems. We introduce an automatic method of proving liveness for randomised parameterised systems under arbitrary schedulers. Viewing liveness as a two-player reachability game (between Scheduler and Process), our method is a CEGAR approach that synthesises a progress relation for Process that can be symbolically represented as a finite-state automaton. The method is incremental and exploits both Angluin-style L*-learning and SAT-solvers. Our experiments show that our algorithm is able to prove liveness automatically for well-known randomised distributed protocols, including Lehmann-Rabin Randomised Dining Philosopher Protocol and randomised self-stabilising protocols (such as the Israeli-Jalfon Protocol). To the best of our knowledge, this is the first fully-automatic method that can prove liveness for randomised protocols.

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Proving Liveness by Backwards Reachability

Cited by 10 publications

References 37 publications

Practical First-Order Temporal Reasoning

Practical First-Order Temporal Reasoning

Systematic Acceleration in Regular Model Checking

Liveness of Randomised Parameterised Systems under Arbitrary Schedulers

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