Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Abstract

This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications

“…Therefore, eDRAM-based PIMs can realize more area-efficient implementation than SRAM-based PIMs. Figure 2 between the proposed PS-nGC and PS-pGC in [28]. Finally, Section 6 presents the con sions of this study.…”

“…Section 4 presents the simulation and experimental results. Section 5 presents a comparison between the proposed PS-nGC and PS-pGC in [28]. Finally, Section 6 presents the conclusions of this study.…”

“…The previous work [28] presented the PS-pGC, which addressed the leakage current issue in the 2T1CAsy gain cell by actively compensating the leakage current. The PS-pGC consists of a 2TAsy gain cell and a p-type PSLC as shown in Figure 5.…”

“…As a result, the need for the capacitor, which is necessary in the conventional 2T1C configuration for data retention, can be eliminated, leading to enhanced efficiency in eDRAM area and density. Additionally, a summary and comparison between the PS-nGC and PS-pGC [28] are provided.…”

“…This paper is organized as follows. Section 2 describes the overview of eDRAM gain cell topologies and limitations of a prior work [28]. Section 3 explains the operating principle and circuit implementation of the proposed PS-nGC and eDRAM macro.…”