PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision

Conti, Francesco; Rossi, Davide; Pullini, Antonio; Loi, Igor; Benini, Luca

doi:10.1007/s11265-015-1070-9

Cited by 70 publications

(47 citation statements)

References 45 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast, this manuscript focuses on the optimization of the standard microarchitectural design patterns for CPU and SoC employed in the IoT and low-end embedded domains. [14] RV32/64/IMAFD 5 in-order 1 yes yes ORCA [15] RV32/IM 4,5 in-order 1 no no BOOM v1 [16] RV64/IMAFD 6 out-of-order up to 3 yes yes BOOM v2 [17] RV64/IMAFD 6 out-of-order up to 4 yes yes PULP Ariane [11] RV32/IMF 6 in-order 1 yes yes PULPino [18] RV32/IMCF 4 in-order 1 yes (+FIFO) no VexRiscv [19] RV32IM 5 in-order 1 yes no mriscv [11] RV32/I 3 in-order 1 no no dualIssueRiscv [10] RV32/IMCF 6 in-order up to 2 yes yes…”

Section: Related Work and Backgroundmentioning

confidence: 99%

“…The PULP project [11] offers single-and multi-core accelerators for embedded platforms implementing the RISC-V ISA [5] where PULPino is the ultra-low-power platform for IoT applications. The PULP project primarily targets ASIC implementations to deliver low-power solutions.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

“…Contributions-This research is focused on the standard microarchitectural components only, without considering any ISA extension since they have been widely explored in the available open literature [10,11] and contributes to the state of the art in two different directions:…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

Scotti

Zoni

2019

JLPEA

View full text Add to dashboard Cite

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.

show abstract

Section: Related Work and Backgroundmentioning

confidence: 99%

Section: Related Work and Backgroundmentioning

confidence: 99%

See 1 more Smart Citation

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

Scotti

Zoni

2019

JLPEA

View full text Add to dashboard Cite

show abstract

“…The proposed BB voltage control strategy has been implemented and validated on the Parallel Ultra-Low-Power platform [4] version 3 (PULPv3) [5], a multi-core near-threshold processor for Internet of Things (IoT) applications.…”

Section: Pulpv3 Socmentioning

confidence: 99%

Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster

Mauro¹,

Rossi²,

Pullini³

et al. 2018

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Self Cite

View full text Add to dashboard Cite

Advanced Ultra-Low Power (ULP) computing platforms can be affected by large performance variations. This phenomenon is mainly caused by process and ambient temperature variations, and it is magnified by the strong Temperature Effect Inversion (TEI) that characterizes devices when operating Near-Threshold (NT) in highly scaled nodes. 28nm UTBB FD-SOI technology supports an extended range of both forward and reverse Body-Bias (BB) voltage. This feature can be efficiently used to reduce margins at design time and compensate variations at runtime. In this paper we propose a BB voltage controller capable to independently probe the maximum frequency of P and N transistors, and leverage a BB voltage adjustment to achieve a user-specified target frequency, minimizing the leakage current. Compared to the case where zero BB is applied to the transistors, the controller achieves up to 23% power reduction exploiting the performance increase originated by TEI, further reducing power by 12% with respect to a symmetric BB approach.

show abstract

“…There have been various efforts to design vision-processing systems targeting CV applications such as [2,[17][18][19], among others. One such effort is Myriad 2 platform from Movidius [20].…”

Section: Introductionmentioning

confidence: 99%

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Mustafa

O’Riordan

Rogers

et al. 2018

J Real-Time Image Proc

View full text Add to dashboard Cite

Computer vision applications are becoming more and more popular in embedded systems such as drones, robots, tablets, and mobile devices. These applications are both compute and memory intensive, with memory bound stalls (MBS) making a significant part of their execution time. For maximum reduction in memory stalls, compilers need to consider architectural details of a platform and utilize its hardware components efficiently. In this paper, we propose a compiler optimization for a vision-processing system through classification of memory references to reduce MBS. As the proposed optimization is based on the architectural features of a specific platform, i.e., Myriad 2, it can only be applied to other platforms having similar architectural features. The optimization consists of two steps: affinity analysis and affinity-aware instruction scheduling. We suggest two different approaches for affinity analysis, i.e., source code annotation and automated analysis. We use LLVM compiler infrastructure for implementation of the proposed optimization. Application of annotation-based approach on a memory-intensive program shows a reduction in stall cycles by 67.44%, leading to 25.61% improvement in execution time. We use 11 different image-processing benchmarks for evaluation of automated analysis approach. Experimental results show that classification of memory references reduces stall cycles, on average, by 69.83%. As all benchmarks are both compute and memory intensive, we achieve improvement in execution time by up to 30%, with a modest average of 5.79%.

show abstract

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision

Cited by 70 publications

References 45 publications

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Contact Info

Product

Resources

About