Pulse-stream circuits for on-chip learning in analogue VLSI neural networks

Woodburn, R.; Reekie, H. Martin; Murray, Alan F.

doi:10.1109/iscas.1994.409208

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…Other approaches for on-chip supervised weight training have been utilized. These approaches include the least-mean-squares algorithm [750], [787], [1025], [1026], weight perturbation [19], [625], [655], [669], [682], [698], [699], [708], [710], [712], [713], [715], [736], [834], [835], [841], [845]- [847], [856], [1078]- [1080], [1098], [1099], [1148], [1304], training specifically for convolutional neural networks [1305], [1306] and others [169], [220], [465], [714], [804], [864], [865], [1029], [1049], [1307]- [1320]. Other on-chip supervised learning mechanisms are built for particular model types, such as Boltzmann machines, restricted Boltzmann machines, or deep belief networks [12], [627], [1135], [1193]<...>…”

Section: A Supervised Learningmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

176

180

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Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brainlike ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled. The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed.

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Section: A Supervised Learningmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

176

180

View full text Add to dashboard Cite

show abstract

“…The currents of M1 and M2 flow to the ground and the value of becomes zero. According to the operation of the synapse circuit described above, a two-quadrant multiplication can be achieved by integrating the output current over the pulsewidth of to obtained the total charges as (7) where is proportional to is proportional to the neuro input , and is a constant. In order to reduce the increased rise time and fall time of , caused by long-distance transmission and inter-chip communication, two inverters are added as shown in Fig.…”

Section: A Synapsementioning

confidence: 99%

“…To enhance the applications of the pulse-stream neural networks, efficient on-chip learning should be implemented in VLSI neural systems. The realization issues of the on-chip learning function in the pulse-stream neural networks were first investigated in [7] where the circuits of some key building blocks have been designed. A complete realization of the neural network with on-chip learning was proposed in [8].…”

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confidence: 99%

Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning

Bor

1998

IEEE Trans. Circuits Syst. II

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In this paper, a CMOS very large scale integration (VLSI) design of the pulsewidth-modulation (PWM) neural network with both retrieving and on-chip leaning functions is proposed. In the developed PWM neural system, the input and output signals of the neural network are represented by PWM signals whereas the multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Therefore, the designed neural network only occupies the small chip area. After compensating the nonideal effects of the switches, the designed circuits have good linearity and large dynamic range. This makes the implementation of onchip learning feasible. To demonstrate the learning capability of the realized PWM neural network, the delta learning rule is realized. An experimental chip with two neurons, twelve synapses, and the associated learning circuits has been fabricated in 0.8m CMOS double-poly double-metal process. The chip area, including the pads, is 3.45 mm 2 3.45 mm. From the measured results, the linearity of synapses versus weight voltages and input pulsewidths can almost be kept under 61% and 60.2%, respectively. The measured results on the three learning examples on AND function, OR function, and simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network. Index Terms-Mixed-mode circuit, neural network, pulsewidth modulation (PWM).

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“…6. 14 Noise, however, cannot be eliminated, and some level of dependence on reference voltages and the vagaries of transistor parameters is fundamental. In addition, analogue circuits require "good" analogue components, such as resistors and capacitors, and analogue signals are intrinsically vulnerable to corruption when transmitted across a chip.…”

Section: Design Of a Simple Two-quadrant Multipliermentioning

confidence: 99%

The Prospects for Analogue Neural VLSI

Murray

Woodburn

1997

Int. J. Neur. Syst.

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In recent years, the efforts of analogue, neural-hardware designers have shifted from generic analogue neurocomputers to "niche" markets in sensor fusion and robotics, and we explain why this is so. We describe the main differences between digital and analogue computation, and consider the advantages of pure analogue and pulsed methods of design. We then investigate some important issues in analogue design of neural machines, namely weight storage (volatile and non-volatile), on-chip learning, and arithmetic accuracy and its relationship to noise. Finally, we outline those areas in which analogue techniques are likely to prove most useful, and speculate as to their likely long-term utility.

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Pulse-stream circuits for on-chip learning in analogue VLSI neural networks

Cited by 8 publications

References 6 publications

A Survey of Neuromorphic Computing and Neural Networks in Hardware

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning

The Prospects for Analogue Neural VLSI

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