Pulser gating: A clock gating of pulsed-latch circuits

Abstract

A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with location of latches, we first extract the gating function of each latch; the gating functions are merged to reduce the amount of extra logic while gating probability is not sacrificed too much. We also have to take account of proximity of latches, because a pulser, which is gated by merged gating function, and its latches have to be physically close for safe delivery of pulse. The heuristic algorithm that considers all three factors (similarity of gating functions, literal count to implement gating functions, and proximity of latches) is proposed and assessed in terms of power saving and area using 45-nm technology.

Exploring the opportunity of optimizing sequencing elements in ASIC designs

“…This implies a new problem, in which we identify a group of latches that can be driven by the same pulser (thus, they are placed nearby) as well as gated at the same time and as often as possible. A preliminary result of solving pulser gating problem [6] demonstrates additional power saving of up to 30% compared with a non-pulser-gated pulsed-latch circuit.…”

“…the former is to minimize the power consumption as pulsers contribute large portion of total power [6] and the latter is to ensure the correct pulse shape [15]. This problem can be solved using a simple heuristic after converting the problem into a graph formulation [6].…”

“…To further reduce the clocking power, clock gating can be implemented via pulsers, instead of clock gating cells, by feeding a gating function to the enable pin of a pulser [6]. This approach is named pulser gating.…”

“…This problem can be solved using a simple heuristic after converting the problem into a graph formulation [6].…”

“…Using pulsed-latches also benefits an appreciable amount of power saving in clock distribu tion [6]. Pulsed-latches have less number of transistors that are triggered by clock signal than flip-flops do; the overhead of pulse generator can be amortized by sharing it among multiple latches.…”