2020 IEEE Workshop on Signal Processing Systems (SiPS) 2020
DOI: 10.1109/sips50750.2020.9195258
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Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs

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Cited by 3 publications
(2 citation statements)
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“…Later on, the authors in [88] proposed a parallel blocklayered approach to the NB-LDPC decoder, further improving performance and reaching 9.795 Mbps. While the GPUs implementations require a few dozen to several hundreds of Watts (65 to 250 W), the authors in [89], [90] were capable of reaching 2.33 Mbps using an embedded system that requires less than 15 W of power.…”
Section: A Gpumentioning
confidence: 99%
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“…Later on, the authors in [88] proposed a parallel blocklayered approach to the NB-LDPC decoder, further improving performance and reaching 9.795 Mbps. While the GPUs implementations require a few dozen to several hundreds of Watts (65 to 250 W), the authors in [89], [90] were capable of reaching 2.33 Mbps using an embedded system that requires less than 15 W of power.…”
Section: A Gpumentioning
confidence: 99%
“…In [89], [90], the authors show that using HLS can reduce the development effort while maintaining a high performance, reaching 38.7 Mbps.…”
Section: B Fpgamentioning
confidence: 99%