Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs

Rebeiro, Chester; Roy, Sujoy Sinha; Mukhopadhyay, Debdeep

doi:10.1007/978-3-642-33027-8_29

Cited by 47 publications

(21 citation statements)

References 19 publications

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“…The work in [22] and [23] are a similar implementation to [11]; however, [11] is a LUTs optimised implementation. In comparison with [21], [22] and [23], our work shows better results than the best results they presented.…”

Section: Implementation Resultsmentioning

confidence: 61%

“…Our proposed ECC processor uses 2 stages pipelining to get 36% improvement in clock frequency speed over [12]. The work in [21] is the previous version of [11]. The work in [22] and [23] are a similar implementation to [11]; however, [11] is a LUTs optimised implementation.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Many high performance ECC processor implementations on FPGA have been reported in the literature; the most relevant are presented in [10], [11], [12], [13], [14], [15], [16], [17], [20], [21], [22], and [23]. The common optimizing technique of high speed designs is the reduction of latency (number of clock Z. U.…”

Section: Introductionmentioning

confidence: 99%

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High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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Abstract-In this paper, a novel high speed ECC processor implementation for point multiplication on Field Programmable Gate Array (FPGA) is proposed. A new segmented pipelined fullprecision multiplier is used to reduce the latency and the LopezDahab (LD) Montgomery point multiplication algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles required. The proposed ECC architecture has been implemented on Xilinx FPGAs Virtex4, Virtex5 and Virtex7 families. To our knowledge, our single multiplier and three multipliers based designs show the fastest performance to date when compared to reported works individually. Our one multiplier based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 µs at 210 MHz), on Virtex5 (4.91 µs at 228 MHz), and on the more advanced Virtex7, (3.18 µs at 352 MHz). Finally, the proposed three multiplier based ECC implementation is the first work reporting the lowest number of clock cycles and the fastest ECC processor design on FPGA (450 clock cycles to get 2.83 µs on Virtex7).

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Section: Implementation Resultsmentioning

confidence: 61%

Section: Implementation Resultsmentioning

confidence: 99%

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High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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“…In comparison with ECC over prime curves (i.e., a single point multiplication [GP08]) and RSA (random-exponent 1024-bit exponentiation [Suz07]) our implementation is by an order of magnitude faster, scales better for higher security levels, and also consumes less resources. However, we are not able to beat the recent binary curve implementation of Rebeiro et al [RRM12] in terms of throughput and performance.…”

Section: Comparison With Related Workmentioning

confidence: 56%

Efficient implementation of ideal lattice-based cryptography

Pöppelmann¹

2017

It - Information Technology

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Digital signatures and public-key encryption are used to protect almost any secure communication channel on the Internet or between embedded devices. Currently, protocol designers and engineers usually rely on schemes that are either based on the factoring assumption (RSA) or on the hardness of the discrete logarithm problem (DSA/ECDSA). But in case of advances in classical cryptanalysis or progress on the development of quantum computers the hardness of these closely related problems might be seriously weakened. In order to prepare for such an event, research on alternatives is required to provide long-term security.In this thesis, we focus on the efficient implementation of such alternative public-key cryptosystems whose security is based on the intractability of certain computational problems on ideal lattices. While an extensive theoretical background exists for lattice-based and ideal latticebased cryptography, not much is known about the efficiency of practical instantiations, especially on constrained and cost-sensitive platforms. We thus investigate novel algorithms and implementation techniques for fast and flexible polynomial multiplication and Gaussian sampling and then use these building blocks to implement public-key encryption and signature schemes. The results provided in this thesis show that lattice-based schemes can be optimized for high performance or resource efficiency on embedded microcontrollers and reconfigurable hardware. Our implementations of a public-key encryption scheme based on the ring learning with errors problems (RLWE) or of the bimodal lattice signature scheme (BLISS) can even outperform classical ECC-and RSA-based implementations.Lattice-based cryptography can also be used to realize homomorphic cryptography that allows computation on encrypted data. However, due to the large parameter sets and complex operations required, even for simple homomorphic evaluation operations, the performance of these schemes is a major issue preventing practical usage. In this thesis we investigate options for acceleration of homomorphic cryptography in a cloud environment using reconfigurable hardware. We implement all evaluation operations of the YASHE homomorphic encryption scheme and propose methods to deal with large ciphertext and key sizes as well as limited memory bandwidth. KeywordsPost-quantum cryptography, public-key cryptosystem, embedded system, microcontroller, FPGA KurzfassungDigitale Signaturen und Public-Key-Verschlüsselung werden für den Schutz nahezu jeder sicheren Kommunikation über das Internet oder zwischen eingebetteten Systemen genutzt. Die Sicherheit basiert dabei entweder auf der Faktorisierungsannahme (RSA) oder der Annahme, dass es schwer ist, das diskrete Logarithmus-Problem (DSA/ECDSA) zu lösen. Durch Fortschritte in der klassischen Kryptoanalyse oder bei der Entwicklung von Quantencomputern könnten diese Probleme allerdings in Zukunft ernsthaft geschwächt oder gelöst werden. Daher ist Forschung zu alternativen Public-Key-Kryptosystemen erforderlich, die in ...

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“…In comparison with ECC over prime curves (i.e., a single point multiplication [21]) and RSA (random-exponent 1024-bit exponentiation [48]) our implementation is by an order of magnitude faster, scales better for higher security levels, and also consumes less resources. However, we are not able to beat the recent binary curve implementation of Rebeiro et al [45] in terms of throughput and performance.…”

Section: Aspectmentioning

confidence: 56%

Towards Practical Lattice-Based Public-Key Encryption on Reconfigurable Hardware

Pöppelmann

Güneysu

2014

Lecture Notes in Computer Science

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Abstract. With this work we provide further evidence that latticebased cryptography is a promising and efficient alternative to secure embedded applications. So far it is known for solid security reductions but implementations of specific instances have often been reported to be too complex beyond any practicability. In this work, we present an efficient and scalable micro-code engine for Ring-LWE encryption that combines polynomial multiplication based on the Number Theoretic Transform (NTT), polynomial addition, subtraction, and Gaussian sampling in a single unit. This unit can encrypt and decrypt a block in 26.19 µs and 16.80 µs on a Virtex-6 LX75T FPGA, respectively -at moderate resource requirements of about 1506 slices and a few block RAMs. Additionally, we provide solutions for several practical issues with Ring-LWE encryption, including the reduction of ciphertext expansion, error rate and constant-time operation. We hope that this contribution helps to pave the way for the deployment of ideal lattice-based encryption in future real-world systems.

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Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs

Cited by 47 publications

References 19 publications

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Efficient implementation of ideal lattice-based cryptography

Towards Practical Lattice-Based Public-Key Encryption on Reconfigurable Hardware

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